DFT Engineer

This is a fully remote position, open to applicants in California.

📋 Description

• Oversee the execution of comprehensive testing architectures utilizing industry-standard CAD tools, such as scan compression, MBIST, and JTAG/boundary scan logic.

• Propel bottom-up hierarchical DFT methodologies for large-scale SoC designs, which includes core-level test wrapping, pattern retargeting, and top-level test integration.

• Take ownership of the DFT strategy and collaborate with foundry interfaces to evaluate defect densities and enhance test-chip yield.

• Lead DFT methodologies for 2.5D/3D multi-stacked die packaging, ensuring test coverage across die-to-die interfaces by adhering to standards like IEEE 1838.

• Support the integration and testability of custom analog mixed-signal blocks while formulating test strategies for non-standard analog macros.

• Drive targets for test coverage, test duration, and yield while influencing micro-architecture to enhance Power, Performance, and Area (PPA).

• Assume responsibility for the final DFT sign-off, encompassing ATPG, test-vector validation, fault simulation, and timing closure during STA for all test modes.

• Contribute to the development and automation of the design flow and establish best practices for testability to ensure first-pass silicon success.

• Assess potential AI-tool partners that may enhance chip-design efficiency.

⛳️ Requirements

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related discipline.

• Over 10 years of professional experience in digital DFT and test architecture.

• Proven history of successful tapeouts on modern process nodes, with a preference for 7nm, 5nm, or newer technologies.

• Extensive knowledge in scan compression, MBIST generation, fault modeling (stuck-at, transition, path delay), and ATPG.

• Profound understanding of physical design challenges in advanced nodes, including multi-patterning, finFET effects, and low-voltage operation, and their implications for test reliability.

• Proficient in Static Timing Analysis (STA) and timing closure for intricate designs in shift and capture test modes.

• Mastery of standard EDA CAD tool suites for DFT implementation and vector generation at an expert level.

• Strong scripting capabilities in Tcl, Python, or Perl for design-flow automation and data analysis.

• Exceptional written and verbal communication skills.

• Experience in managing deliverables from external vendors or design houses.

🏝️ Benefits

• Competitive salary and performance-based incentives.

• Comprehensive health, dental, and vision insurance.

• Opportunities for professional development and career advancement.

• Flexible work environment with options for remote work.

• Generous paid time off and holiday leave.