Staff Physical Design Engineer

This is a fully remote position, open to applicants in United States, +1 more country.

📋 Description

• Lead block-level and top-level physical design activities, encompassing floor-planning, placement, clock tree synthesis (CTS), and routing.

• Meet demanding timing, power, and area (PPA) objectives utilizing advanced timing closure techniques.

• Conduct power grid verification and oversee the analysis and resolution of electromigration and IR drop (EM/IR) issues.

• Create and maintain automation scripts (Tcl/Python) to enhance design flows and methodologies.

• Work collaboratively with physical verification and foundry teams to ensure adherence to design rules and facilitate successful tapeout execution.

• Convert intricate microarchitectures into high-performing, power-efficient silicon.

• Take ownership of the implementation process from netlist to successful foundry tapeout.

⛳️ Requirements

• A Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related discipline.

• 10–15 years of focused experience in physical design.

• Strong grasp of EDA implementation workflows with extensive experience in using Cadence design tools.

• In-depth understanding of static timing analysis (STA) principles and advanced timing closure techniques.

• Proven track record in both top-level and block-level physical design, with a significant advantage for hierarchical floorplanning expertise.

• Expertise in low-power design strategies, debugging, and EM/IR check resolution/power grid verification.

• Strong scripting abilities in Tcl or Python for automating design flows.

• Solid comprehension of advanced process nodes and the physical verification standards related to routing.

• Experience with physical design methodologies, flow setup, and advanced flow evaluations.

• Previous involvement with PDK management or foundry tapeout processes is highly advantageous.

🏝️ Benefits

• Equal employment opportunity employer in the United States.