Senior SoC Architect

This is a fully remote position, open to applicants in Germany.

📋 Description

• Lead the overall technical direction of the EPIC SoC from initial concept to production.

• Foster cross-functional technical collaboration among photonics, analog, digital, technology, and product teams.

• Develop and document the complete product architecture.

• Convert the MRD into a fully developed, internally consistent, and actionable PRD.

• Oversee the architecture of the digital subsystem, which includes core logic, on-chip interconnect fabric, and subsystem partitioning.

• Manage the architecture of the high-speed I/O subsystem, covering SerDes and protocol digital logic for UCIe, PCIe, and Ethernet.

• Integrate the architectures of analog/RF, photonics, packaging, and memory subsystems into a unified full-chip architecture.

• Conduct comprehensive trade-off analyses regarding full-chip performance, power, and area.

• Collaborate with external vendors and third-party IP providers for full-chip validation.

• Coordinate with characterization teams for product characterization.

• Present the integrated architecture and PRD to product management and engineering leadership.

• Maintain ownership of the architecture until sign-off.

⛳️ Requirements

• 7–10 years of experience in SoC or product architecture roles.

• Demonstrated ownership of SoC/product architecture.

• Experience in taking a product from MRD-level requirements to a complete, implementable PRD-level architecture.

• Familiarity with multiple subsystems and involvement in at least one full product architecture cycle.

• Profound expertise in high-speed I/O subsystems.

• Knowledge in high-speed SerDes and protocol digital logic for UCIe, PCIe, and Ethernet.

• Strong experience with digital subsystem and on-chip interconnect fabric architecture.

• Experience in defining digital subsystem partitioning for complex SoCs.

• Excellent cross-domain integration skills encompassing analog, photonic, packaging, and memory architecture inputs.

• Ability to translate marketing/product requirements into actionable engineering architecture specifications.

• Experience in analyzing full-chip performance, power, and area trade-offs.

• Background with third-party IP vendors, external IP evaluation, selection, and design integration partners.

• Familiarity with architecture specification and requirements management tools.

• Knowledge of UCIe, PCIe, and Ethernet protocol/standards documentation and compliance tools.

• Proficiency with architecture and performance modeling tools, including full-chip performance/power models.

• Skills in Python and C++ for modeling, scripting, and analysis.

• Experience using collaboration and documentation platforms.

• Nice to have: previous experience as SoC Chief Engineer.

• Nice to have: knowledge of silicon photonics or electro-optic I/O.

• Nice to have: familiarity with advanced 2.5D/3D packaging and chiplet integration.

• Nice to have: experience collaborating with product management and/or customers on MRD-level requirements.

• Nice to have: experience with CXL or related die-to-die/coherent interconnect standards.

🏝️ Benefits

• Flexible work arrangements and an emphasis on work-life balance.

• Autonomy and opportunities for professional development.

• Continuous learning initiatives.

• Comprehensive benefits package.

• Exceptional insurance coverage.

• Pension plan.

• Virtual stock options.

• An inclusive and supportive work environment.