Senior Power Integrity Engineer

This is a fully remote position, open to applicants in United Kingdom.

📋 Description

• Lead Power Integrity initiatives throughout the hardware development process, from architecture to production.

• Define and enhance board-level and package-level Power Delivery Networks for high-current networking ASICs and associated devices.

• Conduct pre-layout and post-layout PI simulations utilizing industry-standard tools.

• Set target impedance requirements and confirm compliance across all power rails.

• Analyze DC voltage drop, AC impedance, transient response, and performance of power distribution.

• Work alongside PCB layout engineers to refine stackups, plane structures, decoupling strategies, and power routing.

• Collaborate closely with Signal Integrity engineers to ensure SI/PI co-optimization of high-speed interfaces.

• Create power integrity design guidelines and best practices for next-generation networking products.

• Assist in schematic reviews, layout assessments, and design sign-off activities.

• Conduct laboratory measurements and correlation using oscilloscopes, VNAs, power analyzers, current probes, and related equipment.

• Investigate and address PI-related challenges during board bring-up, validation, and production.

• Collaborate with ASIC, FPGA, memory, optics, and power component vendors to enhance overall system performance.

• Propel the continuous improvement of PI methodologies, simulation workflows, and validation processes.

• Fulfill PI sign-off requirements for all networking platforms.

• Reduce power-related issues during bring-up and production phases.

• Enhance the first-pass hardware success rate.

• Facilitate dependable operation of next-generation high-bandwidth networking systems.

• Develop scalable PI methodologies for future DriveNets hardware platforms.

⛳️ Requirements

• B.Sc. or M.Sc. in Electrical Engineering.

• Over 5 years of experience in Power Integrity, Hardware Design, or related fields.

• Strong knowledge of power delivery networks, decoupling methodologies, and target impedance principles.

• Practical experience with PI simulation tools such as Cadence Sigrity PowerSI / OptimizePI, Ansys SIwave, Ansys HFSS, PowerDC, or equivalent.

• Experience in designing high-layer-count PCBs for networking, telecom, server, or data-center applications.

• Familiarity with high-speed digital systems and the interplay between Signal Integrity and Power Integrity.

• Experience with multi-phase voltage regulators, power sequencing, and power management architectures.

• Strong understanding of PCB materials, stackups, and manufacturing limitations.

• Experience in performing lab validation and correlation measurements.

• Proficiency with oscilloscopes, VNAs, power analyzers, current probes, and other laboratory equipment.

• Preferred: Experience with high-performance networking ASICs and switch silicon.

• Preferred: Knowledge of 112G/224G/448G PAM4 SerDes technologies.

• Preferred: Experience with Ethernet systems ranging from 400G to 1.6T and above.

• Preferred: Understanding of package-level PI and advanced packaging technologies.

• Preferred: Familiarity with optical networking platforms and co-packaged optics.

• Preferred: Experience with thermal and mechanical effects on PDN performance.

• Preferred: Knowledge of EMI/EMC considerations in high-density networking systems.

• Preferred: Experience working with ODMs, CMs, and global manufacturing partners.

🏝️ Benefits

• Work on cutting-edge networking systems deployed by leading service providers and cloud operators.

• Influence the architecture of next-generation networking hardware.

• Collaborate with top-tier hardware, ASIC, and software engineers.

• Be part of a rapidly expanding company that is transforming the networking industry.