Senior ASIC Design Engineer

This is a fully remote position, open to applicants in California.

📋 Description

• Execute RTL designs utilizing Verilog/System Verilog for high-speed data pathways and packet processing logic.

• Work in conjunction with verification engineers to develop block- and system-level testing plans.

• Establish timing constraints for RTL components and collaborate with Physical Design engineers to achieve timing closure optimization.

• Assist in post-silicon validation by working alongside hardware, firmware, and software teams to troubleshoot and resolve ASIC challenges.

• Contribute to strategies for performance optimization and power-aware design for Host Fabric Interface subsystems.

⛳️ Requirements

• Bachelor's or Master's degree in Computer Engineering, Electrical Engineering, or a related discipline.

• A minimum of 8 years of post-collegiate experience in digital design.

• Expertise in Verilog and System Verilog.

• Experience in RTL design for high-speed data pathways or packet processing within ASICs.

• Comprehensive understanding of Host Ethernet adapter architectures.

• Familiarity with timing closure and contemporary physical design methodologies.

• Demonstrated capability in system-level debugging and root cause analysis of technical challenges.

• Excellent verbal and written communication abilities.

• Knowledge of Ethernet architecture and networking protocols.

• Previous experience with RTL development for Ethernet host adapters and system debugging.

• Proficiency in designs involving multiple clock domains and asynchronous interfaces.

• Experience with EDA tools such as Design Compiler, Spyglass, or PrimeTime.

🏝️ Benefits

• Equity, cash, and incentives.

• Health, medical, dental, and vision coverage.

• Disability and life insurance.

• Dependent care flexible spending account.

• Accidental injury insurance.

• Pet insurance.

• Generous paid holidays.

• 401(k) with company match.

• Open Time Off (OTO) for regular full-time exempt employees.

• Sick time.

• Bonding leave.

• Pregnancy disability leave.

• Flexible work environment.

• Opportunity to collaborate with prominent figures in the semiconductor industry.