Physical Design Engineer

This is a fully remote position, open to applicants in California.

📋 Description

• Lead the physical implementation of intricate, high-performance blocks and top-level SoC integration from RTL to GDSII.

• Execute floorplanning, power grid design, placement, clock tree synthesis (CTS), routing, and physical verification.

• Drive ambitious Power, Performance, and Area (PPA) objectives.

• Collaborate with architects to influence micro-architecture for improved physical routability and timing closure.

• Take ownership of the final sign-off, including Static Timing Analysis (STA), IR drop analysis, Electromigration (EM), and Physical Verification (DRC/LVS/ERC).

• Develop and automate physical design workflows and establish best practices for synthesis, formal verification (LEC), and parasitic extraction.

• Work alongside digital and analog design teams to integrate custom analog mixed-signal blocks.

• Assess potential AI-tool partners to enhance chip design efficiency.

⛳️ Requirements

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related discipline.

• Over 10 years of industry experience in digital physical design.

• Proven history of successful tapeouts on modern process nodes; experience with 7nm, 5nm, or newer is preferred.

• Expertise in Static Timing Analysis (STA) and achieving timing closure for high-frequency, complex designs.

• Strong understanding of physical design challenges in advanced nodes, including multi-patterning, finFET effects, and low-voltage operation.

• Proficient in power integrity analysis and techniques for noise coupling mitigation.

• Expert-level knowledge of standard EDA tool suites, such as Synopsys Fusion Compiler, IC Compiler II, or Cadence Innovus.

• Strong scripting abilities in Tcl, Python, or Perl.

• Exceptional written and verbal communication skills.

• Experience managing deliverables from external vendors or design houses.

• Preferred: experience in physical design for machine-learning accelerators or large-scale systolic arrays.

• Preferred: experience integrating large custom analog macros and complex power-sequencing requirements.

• Preferred: hands-on experience with multi-voltage domains, UPF/CPF flows, and advanced power-gating techniques.

• Preferred: familiarity with cutting-edge AI tools to expedite chip design.

🏝️ Benefits

• Best-in-class health benefits.

• 401k matching.

• Truly unlimited PTO.

• Complimentary meals in the Mountain View office.

• Massive ownership and a significant opportunity to drive change.

• Comprehensive package.