PCIe ASIC Design Engineer

This is a fully remote position, open to applicants in Texas.

📋 Description

• Spearhead the design and integration of PCIe controllers into next-generation SoCs.

• Take ownership of the complete integration of PCIe IP within intricate ASIC designs.

• Collaborate with IP vendors, architecture teams, verification, physical design, and software groups to deliver reliable PCIe subsystems.

• Lead performance enhancements across the PCIe stack, from PHY tuning to the efficiency of DMA/transaction layers.

• Engage in discussions regarding system architecture and microarchitecture with a focus on I/O and interconnect scalability.

• Oversee silicon bring-up and validation of PCIe links in laboratory settings.

• Work closely with board and firmware teams.

• Troubleshoot functional and performance issues at RTL, gate-level, and silicon stages.

• Ensure adherence to PCIe specifications.

• Participate in interoperability testing as required.

• Mentor junior engineers.

• Assist in defining best practices for PCIe subsystem development.

⛳️ Requirements

• BS/MS in Electrical Engineering, Computer Engineering, or a related discipline.

• Over 10 years of industry experience in ASIC/SoC design, particularly in PCIe controller integration.

• Demonstrated experience in silicon bring-up and debugging of high-speed interfaces.

• Strong understanding of the PCIe protocol stack (PHY, MAC, TLP, DLL), configuration space, and link training processes.

• Practical experience with PCIe verification environments, performance optimization, and power-aware design methodologies.

• Familiarity with PCIe compliance testing, simulation tools (such as VCS, Questa), and laboratory equipment (like protocol analyzers and oscilloscopes).

• Proficient scripting skills in Python, Perl, and TCL.

• Excellent debugging capabilities.

• Strong verbal and written communication skills.

• Preferred experience with PCIe Gen5/Gen6 and advanced retimer or switch solutions.

• Exposure to CXL, CCIX, or other cache-coherent interconnects is a plus.

• Background in data center or AI/ML accelerator architectures is advantageous.

• Experience with emulation and prototyping platforms (e.g., ZeBu, Palladium, HAPS) for validating PCIe subsystems is preferred.

• Candidates must reside within the United States.

🏝️ Benefits

• Equity, cash, and incentives.

• Health benefits.

• Retirement benefits.

• Medical coverage.

• Dental coverage.

• Vision coverage.

• Disability insurance.

• Life insurance.

• Dependent care flexible spending account.

• Accidental injury insurance.

• Pet insurance.

• Generous paid holidays.

• 401(k) with company match.

• Open Time Off (OTO) for regular full-time exempt employees.

• Sick time.

• Bonding leave.

• Pregnancy disability leave.

• Dynamic, flexible work environment.

• Performance-based incentives, including an annual bonus or sales incentives (depending on role).