Hardware ASIC Packaging SI/PI Simulation and Design Lead

This is a fully remote position, open to applicants in California, +6 more states.

📋 Description

• Create, document, and execute design guidelines for ultra-high-speed signaling.

• Evaluate substrate signal integrity and power integrity across interposer, substrate, and PCB.

• Work in collaboration with layout teams to devise optimal packaging solutions.

• Design, document, and develop ASIC packages for high-volume, high-quality releases.

• Conduct post-layout extraction and reporting.

• Partner with system stakeholders, vendors, and design leads to address complex technical challenges.

• Establish processes, methods, and tools for intricate ASIC/package developments.

• Lead or engage in discussions regarding chip architecture and high-performance ASIC design.

• Review complex IC and analog/mixed-signal circuit designs.

• Mentor and assist the signal integrity team and junior engineers.

• Advocate for packaging and hardware teams to fulfill technical specifications.

• Foster design reviews, postmortems, and continuous improvement across multidisciplinary engineering teams.

⛳️ Requirements

• Bachelor’s degree in Electrical Engineering with 8+ years of relevant signal and power integrity experience, or a Master’s degree in Electrical Engineering with 6+ years of relevant experience, or a PhD in Electrical Engineering with 3+ years of relevant experience.

• Familiarity with high-speed design principles, including Transmission Line Theory, electromagnetics, scattering parameters, and impedance network analysis.

• Experience applying high-speed design principles to 56G PAM4 SerDes architectures, channel modeling, and BER prediction.

• Proficiency in pre- and post-layout SI/PI simulations.

• Expertise with industry-standard EDA tools such as Cadence Sigrity, Ansys HFSS, and Keysight ADS.

• Background in conducting detailed layout reviews and physical design validation using Cadence APD and Ansys EM flows.

• Experience with SPICE for circuit-level analysis, signal modeling, and performance validation.

• Preferred: ability to convey technical concepts to diverse audiences.

• Preferred: experience with HBM or high-speed memory interface signal integrity.

• Preferred: experience with UCIe or proprietary die-to-die interfaces.

• Preferred: experience with advanced packaging technologies such as CoWoS, EMIB, and interposer-based designs.

• Preferred: experience with Vector Network Analysis.

• Preferred: experience with IBIS.

🏝️ Benefits

• Medical, dental, and vision insurance.

• 401(k) plan with a Cisco matching contribution.

• Paid parental leave.

• Short- and long-term disability coverage.

• Basic life insurance.

• Cisco restricted stock unit grants may be available, vesting following continued employment.

• 10 paid holidays per full calendar year.

• 1 floating holiday for non-exempt employees.

• Paid day off for the employee’s birthday.

• Paid year-end holiday shutdown.

• 4 paid days off for personal wellness.

• 16 days of paid vacation time per full calendar year for non-exempt employees.

• Flexible vacation time off program with no defined limit for eligible exempt employees.

• 80 hours of sick time off provided on hire date and each January 1st thereafter.

• Up to 80 hours of unused sick time carried forward.

• Additional paid time away for critical or emergency family issues.

• Optional 10 paid volunteer days per full calendar year.

• Annual bonuses for non-sales roles, subject to Cisco policies.

• Performance-based incentive pay for sales-plan employees.