
ASIC Design Engineer
Posted Sep 2

Posted Sep 2
This is a fully remote position, open to applicants in Costa Rica.
β’ Develop advanced Ethernet protocols for next-generation Ethernet ASICs.
β’ Create microarchitecture specifications.
β’ Establish timing constraints for RTL blocks and collaborate with Physical Design engineers on timing optimization.
β’ Partner with verification engineers to formulate block- and system-level test plans, ensuring sufficient design coverage.
β’ Collaborate with hardware, firmware, and software engineers to address post-silicon ASIC challenges.
β’ B.S. or M.S. degree in Computer or Electrical Engineering.
β’ Over 3 years of professional experience in digital design.
β’ Expertise in Verilog and System Verilog.
β’ Relevant experience with timing closure.
β’ Knowledge of contemporary physical design methodologies.
β’ Proven ability in system-level debugging and identifying the root causes of technical issues.
β’ Excellent verbal and written communication skills.
β’ Preferred: Experience with Ethernet architecture and networking protocols.
β’ Preferred: Familiarity and experience in designing Ethernet protocols suitable for Ethernet adapters and switches.
β’ Preferred: Background in multiple-clock designs and asynchronous interfaces.
β’ Performance incentives.
β’ Equity participation.
β’ Additional benefits based on geographic location.
β’ Paid holidays according to geographic location.
β’ Flexible work arrangements depending on geographic location.
AECOM
Jabil
WBS
WBS Training
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