Silicon Physical Design Engineer V

This is a fully remote position, open to applicants in United States.

📋 Description

• Establish and sustain PPRTL and PTPX power analysis workflows for average and time-based/peak power assessments.

• Create and oversee activity inputs (FSDB/VCD/SAIF) derived from RTL and gate-level simulations.

• Manage long-waveform and windowed analyses.

• Compare RTL-level power estimates against gate-level signoff power and elucidate discrepancies.

• Generate power breakdowns on a per-block, per-hierarchy, and per-workload basis.

• Identify primary power contributors and areas of clock/datapath inefficiency.

• Suggest and assess power reduction strategies, encompassing clock gating efficiency, datapath gating, memory power, and idle leakage.

• Automate workflows and reporting utilizing TCL, Python, and Make-based build systems.

• Incorporate automation into regression and continuous integration processes.

• Document methodologies and assist design teams in interpreting outcomes.

• Conduct PPA optimization using Fusion Compiler.

• Execute RTL and netlist-level power analyses.

• Post-process and script report log files for format conversion, data analysis, and information extraction.

• Configure, execute, troubleshoot, and analyze ASIC workflows including synthesis, physical design, power, and timing.

• Implement selected blocks at RTL and UPF levels.

• Clearly document and communicate findings.

⛳️ Requirements

• Over 10 years of experience as an ASIC Power Engineer, CAD Engineer, or Physical Design Engineer.

• Proficiency with power estimation tools and synthesis, along with some background in physical design.

• Understanding of power trade-offs in design and back-end implementations.

• Practical experience in scripting and data analysis.

• Hands-on production experience with Synopsys tools (PPRTL, PTPX/PrimePower, VCS, Verdi, DC, ICC, FC) and/or Cadence tools (Joules), PowerArtist.

• Ability to troubleshoot simulation-to-power flow issues comprehensively.

• Strong scripting capabilities in TCL, Python, and Excel-based scripting and data post-processing tools, including model fitting, data visualization, and analysis.

• Proficient working with Linux and large compute/job-scheduling environments.

• Experience in low power design, tools, and methodologies, including UPF power intent specifications.

• Knowledge of silicon power characterization, including some experience in power modeling and profiling at the IP/SoC level.

• Interest or experience in machine learning hardware tailored for AR/VR products.

• Bachelor’s degree in Electrical Engineering, Computer Science, or equivalent experience.

• Must be able to work during Pacific Time (PST) hours.

🏝️ Benefits

• Comprehensive employee benefits coverage at 100%, including Medical.

• Paid Time Off (PTO).

• Holiday Pay.

• 401K Plan.