Senior Circuit Timing Engineer

This is a fully remote position, open to applicants in California.

📋 Description

• Engage in innovative processor design utilizing deep submicron technologies.

• Create advanced circuits focused on hardware security, adaptive clocking, and power management solutions.

• Lead timing analysis and signoff for custom circuit macros, which includes digital, semi-custom, and analog mixed-signal designs.

• Validate timing through the use of STA tools such as Nanotime, PrimeTime, Tempus, and SPICE simulation tools.

• Collaborate with cross-functional teams to enhance power, performance, area, and reliability of next-gen products.

• Develop timing models and methodologies for cutting-edge custom macro designs.

• Conduct transistor-level circuit design, including timing, schematic entry, and layout delivery.

• Incorporate AI/ML methodologies into the design process.

• Collaborate with PD, DFX, Clocks, and other teams regarding timing signoff strategy, constraints, timing and power convergence, DFT, and timing ECO implementation.

⛳️ Requirements

• A BSEE/MS is preferred in Electrical or Computer Engineering, or equivalent experience.

• A minimum of 6 years of digital circuit design experience for Master's degree holders and 8 years for Bachelor's degree holders.

• Strong understanding of deep submicron process challenges and digital circuit design techniques.

• Proficiency in industry-standard STA tools, including Nanotime, Primetime, Tempus, and other timing analysis tools.

• Practical experience with SPICE simulations, EM/IR analysis, and static timing analysis/closure.

• Demonstrated experience in timing constraints generation and management.

• Expertise in analyzing and resolving timing paths via ECOs, including addressing crosstalk and glitch noise.

• Solid grasp of extracted timing models and the application of .libs in Primetime.

• Understanding of process variation effect modeling and design convergence in multi-GHz deep submicron technology.

• Proven experience and ownership across the entire silicon design flow, from micro-architecture and RTL design to back-end execution, including Custom/Semi-Custom Circuit Design, Synthesis, Auto Place and Route, STA, and PVerf.

• Demonstrated capability in post-silicon characterization and debugging.

• A successful history of independently driving and delivering complex features from initial conception to tape-out and validation.

• Familiarity with timing closure strategies for digital logic/macros within AMS designs/IPs.

🏝️ Benefits

• Equity

• Comprehensive benefits package