Principal ASIC Integration Engineer

This is a fully remote position, open to applicants in Europe.

📋 Description

• Collaborate with electrical engineering teams to establish requirements, assess architectural options, and develop specifications for ASICs.

• Lead system-level trade-off analyses focusing on performance, power, die size, unit cost, manufacturability, yield, and readiness for production.

• Oversee the technical evaluation, selection, and integration of third-party semiconductor IP, including analog, compute, and memory components.

• Represent the electrical engineering team in technical discussions with foundries, OSAT partners, and IP suppliers.

• Monitor semiconductor technology roadmaps and address manufacturing constraints and bottlenecks in collaboration with external partners.

• Influence the selection of process nodes and PDKs based on factors such as performance, power, cost, yield, and foundry maturity.

• Promote Design-for-Cost, Design-for-Manufacturing, Design-for-Assembly, and Design-for-Yield considerations throughout the architecture and design phases.

• Guide decisions related to floorplanning, die-size optimization, pin count and placement, and packaging.

• Provide technical insights for semiconductor cost models, considering wafer economics, OSAT locations, packaging, test time, yield, and unit-cost drivers.

• Collaborate with test and validation engineers to develop strategies that maximize fault coverage while minimizing testing time and production costs.

• Incorporate supply-chain resilience and multi-sourcing flexibility into architectural and manufacturing decisions.

• Analyze production-line yields and silicon test data to identify opportunities for continuous improvement.

• Work with both technical and commercial stakeholders throughout the entire ASIC lifecycle, from architecture and technology selection to tape-out, manufacturing, testing, and yield optimization.

⛳️ Requirements

• A minimum of 8 years of experience in ASIC microarchitecture, design, or SoC design in an electrical engineering context.

• Proven track record with multiple successful ASIC or SoC tape-outs.

• Experience guiding designs through the complete development lifecycle.

• Strong grasp of ASIC and SoC architecture and microarchitecture, including system-level architectural trade-offs.

• Practical experience in evaluating, selecting, and integrating third-party semiconductor IP, including analog, compute, and memory components.

• Familiarity with semiconductor foundry processes, process nodes, and PDKs.

• Knowledge of semiconductor packaging, assembly, testing methodologies, fault coverage, and production-test optimization.

• Understanding of yield fundamentals, silicon test data, production-line yield analysis, and yield optimization.

• Familiarity with Design-for-Cost, Design-for-Manufacturing, Design-for-Assembly, and Design-for-Yield principles.

• Knowledge of wafer economics, OSAT operations, packaging and test costs, and semiconductor unit-cost drivers.

• Ability to assess technical decisions considering system BOM costs, manufacturing feasibility, production timelines, and supply-chain risks.

• Comfortable collaborating with foundries, OSAT partners, IP vendors, and multidisciplinary internal teams.

• Willingness to travel internationally for business, particularly to Denmark.

🏝️ Benefits

• Equal opportunities in recruitment, career development, and leadership.

• Engagement in international engineering projects expected to last at least one year, with the potential for a one-year extension.