This is a fully remote position, open to applicants in California.

📋 Description

• Establish and take charge of a scalable CPU physical design methodology, encompassing synthesis, floorplanning, power planning, place and route, CTS, extraction, STA, SI, EM/IR, and physical verification.

• Investigate AI/ML-enhanced physical design tools.

• Initiate synthesis and place-and-route processes for CPU partitions.

• Create the new program RM flow.

• Propel automation, constraints, quality metrics, signoff criteria, dashboards, checkers, and debugging workflows.

• Collaborate with architecture, RTL, circuit, DFT, CAD, program, data, and EDA vendor teams to facilitate advanced nodes and integrate AI/ML within physical design.

⛳️ Requirements

• Over 10 years of experience in ASIC/SoC/CPU development, particularly focused on high-performance CPUs or similarly intricate digital designs.

• Extensive knowledge in RTL-to-GDS implementation and signoff, covering timing closure, power optimization, SI, EM/IR, extraction, and physical verification.

• Proven experience in developing or managing physical design methodologies, automation, or CAD flows.

• Proficient in Tcl, Python, Perl, or comparable scripting languages.

• Strong technical leadership skills to influence teams, mentor engineers, and establish standards across geographically dispersed organizations.

• Must be eligible to access U.S. export-controlled technology, fulfilling compliance with relevant U.S. export laws and potential citizenship/permanent residency or prior licensing requirements.