This is a fully remote position, open to applicants in Spain.

📋 Description

• Validate the next generation of high-performance RISC-V CPU cores

• Collaborate closely with CPU architects, RTL designers, and software engineers

• Create and implement verification strategies

• Establish robust test environments and test benches

• Design comprehensive test plans

• Conduct constrained-random testing, assertions, and functional coverage

• Troubleshoot RTL and simulation failures utilizing waveforms and debugging tools

• Identify critical corner cases in contemporary out-of-order processors

• Take ownership of significant portions of the verification process

• Drive issues to resolution

• Engage throughout the design lifecycle from specification to silicon

⛳️ Requirements

• Over 6 years of experience in design verification for CPUs, SoCs, ASICs, or other intricate digital designs

• Extensive experience with SystemVerilog and UVM, encompassing testbench development, constrained-random testing, assertions, and functional coverage

• Familiarity with CPU architecture and/or microarchitecture, including pipelines, out-of-order execution, caches, load/store mechanisms, branch prediction, and instruction scheduling

• Proficient in debugging RTL and simulation failures using waveforms and standard simulation/debug tools

• Strong programming skills in C/C++ or Python

• Capability to collaborate effectively with RTL designers, architects, and fellow verification engineers

• Eligible to access U.S. export-controlled technology, or capable of obtaining the necessary license approval when applicable