Lead DFT Engineer

This is a fully remote position, open to applicants in Canada, +1 more country.

📋 Description

• Define and execute the comprehensive DFT architecture for intricate SoCs, encompassing Hierarchical DFT, Scan compression, Boundary Scan, and MBIST.

• Create In-System Test (IST) and power-on self-test (POST) methodologies for chip health monitoring in remote edge data centers.

• Supervise scan insertion, ATPG (Stuck-at, Transition, Path Delay), as well as Memory/Logic BIST activities.

• Collaborate with Design, Physical Design, and Yield teams to attain high test coverage while reducing area overhead and power consumption, including performing timing analysis.

• Lead silicon bring-up and troubleshooting on ATE to identify the root causes of silicon failures and enhance test duration.

⛳️ Requirements

• Over 12 years of experience in DFT, with a minimum of 2 years in a leadership or principal capacity.

• Bachelor’s degree in a relevant field.

• Proficient in Synopsys TestMAX, Siemens/Mentor Tessent, or Cadence Modus.

• Extensive knowledge of MBIST with repair functionalities, SCAN, IJTAG (IEEE 1687), and boundary scan (IEEE 1149.1/6).

• Demonstrated success with FinFET nodes (7nm, 5nm, or below).

• Experience in managing DFT for multi-voltage/power-gated designs.

🏝️ Benefits

• Competitive salary and performance-based bonuses.

• Comprehensive health and wellness benefits.

• Opportunities for professional development and continuing education.

• Flexible work hours and remote work options.