Hardware ASIC Packaging SI/PI Simulation and Design Lead

This is a fully remote position, open to applicants in California.

📋 Description

• Develop, document, and execute design guidelines for ultra-high-speed signaling.

• Evaluate substrate signal integrity and power integrity across interposer, substrate, and PCB.

• Work collaboratively with layout teams to create optimal SI/PI solutions.

• Design, document, and produce ASIC packages for high-volume, high-quality releases.

• Conduct post-layout extraction and reporting.

• Partner with system collaborators, vendors, and design leaders to address complex technical challenges.

• Establish processes, methods, and tools for intricate ASIC/package development.

• Lead or engage in discussions regarding chip architecture and the definition, architecture, and design of high-performance ASICs.

• Review complex IC and analog/mixed-signal circuit designs.

• Mentor and assist signal integrity team members and junior engineers.

• Influence packaging and hardware teams to adhere to technical specifications and foster innovative solutions.

• Encourage design reviews, postmortems, and continuous improvement across multidisciplinary engineering teams.

⛳️ Requirements

• Bachelor's degree in Electrical Engineering with 8+ years of relevant signal and power integrity experience, or a Master's degree in Electrical Engineering with 6+ years of relevant experience, or a PhD in Electrical Engineering with 3+ years of relevant experience.

• Proficient in high-speed design principles, including Transmission Line Theory, electromagnetics, scattering parameters, and impedance network analysis.

• Experience applied to 56G PAM4 SerDes architectures, channel modeling, and BER prediction.

• Familiarity with pre- and post-layout SI/PI simulation using Cadence Sigrity, Ansys HFSS, and Keysight ADS.

• In-depth layout review and physical design validation experience utilizing Cadence APD and Ansys EM flows.

• SPICE experience for circuit-level analysis, signal modeling, and performance validation.

• Preferred: ability to convey technical concepts to varied audiences both verbally and in writing.

• Preferred: experience with HBM or high-speed memory interface SI.

• Preferred: experience with UCIe or proprietary die-to-die interfaces.

• Preferred: advanced packaging experience, including CoWoS, EMIB, and interposer-based 2.5D ASIC packaging.

• Preferred: experience with Vector Network Analysis.

• Preferred: familiarity with IBIS.

🏝️ Benefits

• Medical, dental, and vision insurance.

• 401(k) plan with a Cisco matching contribution.

• Paid parental leave.

• Coverage for short- and long-term disability.

• Basic life insurance.

• Cisco restricted stock unit grants may be available.

• 10 paid holidays each full calendar year.

• 1 floating holiday for non-exempt employees.

• 1 paid day off for the employee’s birthday.

• Paid year-end holiday shutdown.

• 4 paid days off for personal wellness.

• 16 days of paid vacation per full calendar year for non-exempt employees.

• Flexible vacation time off program with no defined limit for eligible exempt employees.

• 80 hours of sick time off granted on hire date and each January 1st.

• Up to 80 hours of unused sick time can be carried forward.

• Additional paid time off for critical or emergency family matters.

• Optional 10 paid volunteer days per full calendar year.

• Annual bonuses for non-sales roles, subject to Cisco policies.