FPGA Engineer – Chip Design

This is a fully remote position, open to applicants in India.

📋 Description

• Create realistic engineering evaluation assignments involving RTL design, functional verification, synthesis, physical design, and sign-off.

• Develop reference implementations using Verilog, SystemVerilog, or VHDL, accompanied by testbenches, constraints, and expected outcomes.

• Establish clear grading standards and validation techniques that align with industry-standard engineering expectations.

• Assess AI-generated RTL, testbenches, hardware designs, and implementation outcomes to pinpoint functional errors and design deficiencies.

• Troubleshoot verification failures, coverage gaps, timing violations, and suboptimal power, performance, and area choices.

• Review designs for functional accuracy, timing requirements, resource utilization, and quality of implementation.

• Set up and sustain EDA-based environments that allow AI agents to perform realistic chip-design workflows.

• Utilize relevant tools from Synopsys, Cadence, Siemens, AMD/Xilinx Vivado, or Intel Quartus.

• Create tasks that evaluate synthesis quality, place-and-route outcomes, static timing analysis, and timing closure.

• Recognize recurring failure patterns in AI agents and transform them into new evaluation scenarios and more complex engineering tasks.

• Collaborate with engineering and research teams to enhance evaluation environments, testing procedures, and technical benchmarks.

• Automate design processes, testing, and result analysis with scripting languages.

• Document reference solutions, design assumptions, failure scenarios, and evaluation approaches.

⛳️ Requirements

• 3–5 years of practical experience in ASIC or FPGA design, ideally across various stages of the digital design flow.

• B.E./B.Tech or M.Tech in Electrical Engineering, Electronics Engineering, VLSI, or a similar field.

• Proficient RTL development capabilities in Verilog, SystemVerilog, or VHDL.

• Hands-on experience with design verification, including testbench creation, debugging, coverage analysis, and UVM or similar methodologies.

• Familiarity with EDA tools and workflows from Synopsys, Cadence, Siemens, AMD/Xilinx, or Intel.

• Comprehension of logic synthesis, place-and-route, static timing analysis, timing constraints, and timing closure.

• Strong engineering judgment in assessing power, performance, and area (PPA) trade-offs.

• Proven experience in managing at least one project from specification to implementation or tape-out.

• Excellent debugging, analytical, and problem-solving skills, with the ability to articulate precisely why a design is successful or fails.

• Knowledge of Python, Tcl, or Perl for design-flow automation is a plus.

• Experience with open-source tools such as Yosys, OpenROAD, Verilator, or cocotb is advantageous.

• Interest in AI engineering evaluations, reinforcement-learning environments, or model post-training is a plus, though not mandatory.

🏝️ Benefits

• Comprehensive health insurance coverage.

• Opportunities for professional development and training.

• Flexible working hours and remote work options.

• Collaborative and innovative work environment.