Senior Director, Engineering

This is a fully remote position, open to applicants in Canada.

📋 Description

• Oversee the architecture, circuit design, and physical implementation of memory compilers for SRAM, ROM, register files, and dual-port RAM.

• Specify bitcell selection, peripheral architecture, redundancy and repair strategies, and assist circuits to meet PPA objectives.

• Enhance Vmin, leakage, performance, area, and yield optimization across PVT corners, process variations, and aging effects.

• Manage the technical roadmap for the memory portfolio, encompassing compiler variants, new process nodes, features, and methodology enhancements.

• Establish design, verification, and signoff methodologies.

• Conduct design and layout reviews, SPICE/FastSPICE characterization, statistical/Monte Carlo analysis, BIST/repair, DFT, and physical verification processes.

• Lead silicon validation efforts, including test chip development, testing, and reporting.

• Mentor and develop a team of memory design engineers across circuit design, layout, characterization, and compiler automation.

• Set team objectives, conduct technical evaluations, develop career trajectories, and manage engineering resources across projects and customer engagements.

• Spearhead presales activities, present Silvaco's memory portfolio, and formulate technical proposals.

• Convert customer SoC requirements into compiler specifications and PPA commitments.

• Collaborate with sales, field application engineers, and product management on RFQs, technical assessments, and benchmarking efforts.

• Facilitate technical workshops, address technical inquiries, and assist in audit-style reviews.

• Conduct PPA analysis and competitive benchmarking against foundry and third-party memory IP.

• Perform architecture trade-off analyses and convert findings into datasheets, application notes, and technical white papers.

• Act as the primary technical liaison for strategic customers throughout evaluation, integration, tapeout, and silicon validation processes.

• Guide integration debugging, silicon correlation discussions, and root-cause analysis of customer challenges.

• Collaborate with design, characterization, CAD, and product teams.

• Represent Silvaco at foundry partner meetings and industry conferences as required.

⛳️ Requirements

• BS, MS, or PhD in Electrical Engineering, Computer Engineering, or a related discipline.

• Over 10 years of experience in embedded memory design, with successful production tapeouts of SRAM and at least two of the following: ROM, 1-port register file, 2-port register file, dual-port RAM.

• Extensive knowledge in bitcell-level circuit design, memory peripherals, self-timed paths, sense amplifier design, and assist circuit techniques.

• Practical experience across various process nodes, including FinFET and/or advanced sub-7nm nodes.

• Strong proficiency in SPICE simulation, statistical and Monte Carlo analysis, Vmin/yield modeling, and reliability assessments (BTI/HCI/EM).

• Familiarity with memory compiler architecture and automation, including the generation of .lib, LEF, GDS, Verilog, and CDL views.

• Hands-on experience with DFT/scan tools like Tessent and FastScan.

• Knowledge of power integrity signoff using RedHawk or equivalent solutions.

• Experience with layout verification processes, including DRC, LVS, and parasitic extraction.

• Understanding of RTL/Verilog modeling for memory compilers, test chip definition, silicon correlation, and SDK/automation development for compiler view generation.

• Proven leadership experience managing a team of 6 or more memory designers.

• Demonstrated success in customer-facing technical roles, including presales, PPA negotiations, and integration support.

• Excellent written and verbal communication abilities.

• Proficiency in Python, TCL, Perl, and Linux-based design environments.

• Experience working with AI tools such as Claude, OpenAI, and Gemini.

• Prior experience presenting at industry events or contributing to memory IP standards.

• Direct experience engaging with foundry partners regarding PDK, bitcell qualification, and reference flow alignment.

• Preferred: experience leading memory compiler initiatives at an IP vendor, foundry, or large semiconductor corporation.

• Preferred: background in low-power memory design for mobile, IoT, automotive, or AI/ML accelerator applications.

• Preferred: experience with multi-port memory architectures beyond 2-port and specialty memories.

🏝️ Benefits

• Equity, bonuses, commission, or other forms of compensation may be provided depending on the position.

• Medical, financial, and additional benefits.