R&D ASIC Engineer

This is a fully remote position, open to applicants in France.

📋 Description

• Define and specify ASIC architectures, focusing on both functional and testability aspects.

• Model in RTL using VHDL and Verilog, emphasizing ASIC module design.

• Verify RTL models within an ASIC environment utilizing UVM.

• Implement and simulate Design for Test (DFT) and ATPG methodologies.

• Conduct physical design of the circuit up to GDSII, which includes synthesis, place-and-route, DRC, and LVS.

• Design and integrate RTL/IP modules and top-level designs (Top).

• Virtually verify modules and ASIC top-level designs, including RTL and timing validation.

• Implement, generate, simulate, and debug ATPG patterns.

• Perform synthesis, static timing analysis (STA), and formal verification tasks.

• Define placement and timing constraints effectively.

• Execute physical implementation and verification processes such as floorplanning, partitioning, pad ring, place-and-route, DRC, LVS, and EMIR.

• Provide ongoing support to teams and clients following Tape-Out.

⛳️ Requirements

• Ideally, a graduate from an engineering school or possess a Master’s degree (Bac+5) in (micro)electronics.

• All levels of experience are welcome, ranging from entry-level to expert.

• The position is also open to seasoned technicians specializing in ASIC design, with a minimum of 10 years of experience.

• Experience with ASICs, MPUs, MCUs, or FPGAs, including technologies such as ARM, RISC-V, CML, NoC, PCIe, CXL, DDR, HBM, USB, or I3C.

• Proficient in VHDL and/or SystemVerilog, Verilog, or SystemC.

• Experience with IPs, Top-level design, testbench, OVM, and UVM methodologies.

• Competent in RTL/IP module design and top-level integration/creation.

• Proficient in virtual verification of modules and ASIC tops, RTL, and timing, using C, C++, and UVM.

• Skilled in Design for Test, including the implementation, generation, simulation, and debugging of ATPG patterns.

• Proficient in synthesis, STA, and formal verification techniques.

• Capable of defining placement and timing constraints.

• Skilled in implementation and physical verification processes: floorplanning, partitioning, pad ring, place-and-route, DRC, LVS, EMIR, package constraints, DEF, LEF, and GDSII.

• Familiarity with ASIC EDA tools from Cadence, Siemens, and Synopsys.

• Proficient in test automation using Tcl and Python.

🏝️ Benefits

• Availability of a remote work policy in France and internationally.

• Policies promoting professional equality, parental support, work-life balance, and sustainable mobility.

• Access to certifications and training upon request.

• Customized support from your career manager.

• A comprehensive 9-month onboarding program.

• Participation in an employee shareholding plan.

• Discounts on various activities and services.

• Partial reimbursement for holiday expenses.

• Reimbursement for your sports or cultural membership fees.

• An inclusive culture within a multicultural and disability-friendly environment.

• Engagement in solidarity initiatives with partner organizations.

• A commitment to reducing environmental impact.