This is a fully remote position, open to applicants in California.

📋 Description

• Perform full-custom analog/mixed-signal layout for essential blocks, transitioning from schematics to manufacturable layouts.

• Create optimized block and top-level floorplans, along with placement and routing strategies.

• Achieve a balance among area, parasitics, matching, congestion, and integration into the D2D PHY.

• Enhance resistance/capacitance parasitics, coupling, IR drop, and electromigration to fulfill precision, noise, timing, and power objectives.

• Fulfill DRC, LVS, ERC, DFM, and Antenna specifications.

• Assist in post-layout extraction and simulation processes.

• Contribute to layout methodology and develop automation scripts using Python, Tcl, SKILL, etc., as an additional asset.

• Integrate high-speed analog/mixed-signal IP into intricate D2D PHYs across digital, analog, and I/O domains.

⛳️ Requirements

• Proven analog/mixed-signal IC layout engineer with a solid full-custom layout experience in high-speed blocks, including PLLs, VCOs, ADCs, DACs, LDOs, comparators, clock generators, and high-speed I/Os.

• Skilled in Synopsys Custom Compiler or Cadence Virtuoso tools.

• Proficient in Synopsys ICV or Siemens Calibre for DRC, LVS, ERC, DFM, and Antenna physical verification.

• Extensive experience with CMOS/FinFET nodes, preferably within TSMC or Samsung 12nm–2nm processes.

• Experience in delivering silicon outcomes.

• Strong understanding of EM/IR, ESD, and latch-up considerations in mixed-signal layouts.

• Typically possess a BSEE degree or equivalent experience.

• Approximately 10+ years of experience in analog/mixed-signal layout.

• Capable of independently managing complex blocks while effectively collaborating with circuit designers.

• Must be eligible to access U.S. export-controlled technology; employment may be contingent on citizenship/permanent residency status or prior license approval.