Design Verification Engineer

This is a fully remote position, open to applicants in Romania.

📋 Description

• Design and sustain SystemVerilog/UVM verification environments for SerDes and PHY components

• Create testbenches, functional coverage models, and assertions

• Execute simulations, assess failures, and troubleshoot both RTL and testbench challenges

• Work collaboratively with design, architecture, and analog teams on both block-level and top-level verification

• Validate high-speed SerDes IP utilized in PCIe, Ethernet, and other industry-standard interfaces

⛳️ Requirements

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field

• 0–5 years of experience in digital design or verification (including internships, academic projects, or industry experience)

• Proficient understanding of SystemVerilog and basic knowledge of UVM principles

• Strong foundation in digital design concepts: synchronous logic, FSMs, pipelining, and clock domain crossing

• Excellent analytical and debugging skills — you thrive on resolving issues

• Effective communication skills in English (both spoken and written)

• Candidates should ideally have the ability to reside in Iași

🏝️ Benefits

• [Details of benefits can be added here]