Analog Engineer, Senior

This is a fully remote position, open to applicants in Germany.

📋 Description

• Take responsibility for schematic-level design and post-layout validation of high-speed transmitter signal paths and linear chains, which encompass DAC-based output stages, high-swing/high-speed driver interfaces, ESD, and bump.

• Collaborate with management, system designers, and lab validation teams to refine architecture and fulfill standard and product specifications.

• Assess circuit topologies and propose implementations based on considerations of power, area, bandwidth, and technological tradeoffs.

• Work alongside layout and design engineers to ensure designs are delivered through complete GDSII integration.

• Lead extraction-based post-layout simulations and verify transmitter performance across various process, voltage, and temperature conditions.

• Conduct root-cause analysis of design and post-layout performance discrepancies and implement corrective design measures.

• Monitor block and transmitter-level performance and power against established targets.

• Convert architecture and system requirements into transmitter designs while incorporating design and silicon insights into future architectural developments.

• Develop and utilize behavioral/design models, including MATLAB and Verilog-A.

• Collaborate with lab validation teams to align silicon outcomes with simulations and assist in test-chip, product initiation, and characterization.

• Offer technical advice and mentorship to junior design and layout engineers.

• Regularly report status and share experiences with the team.

⛳️ Requirements

• M.S./PhD in Electrical Engineering, Computer Engineering, or a related scientific field.

• Over 10 years of industry experience in designing high-speed analog, mixed-signal, or SerDes transmitter circuits using advanced CMOS technologies, covering schematic design through post-layout verification.

• Proficient in transmitter circuit building blocks, including DAC-based output stages, serializers or multiplexers, output drivers, and clocking circuits.

• Experience in executing post-layout and extraction-based simulations across varying process, voltage, and temperature conditions.

• Proven track record of delivering analog circuit designs validated through silicon.

• Familiarity with Cadence, Mentor, or Synopsys tools, such as Virtuoso, Calibre, STAR-RC, and MMSIM.

• Strong written and verbal communication skills.

• Capability to work autonomously as well as collaboratively within a team setting.

• Experience with 224G or 448G PAM4 or PAM6 SerDes and relevant OIF-CEI or IEEE standards.

• Background in contributing to transmitter architecture using MATLAB, Verilog-A, or C++.

• Knowledge of signal integrity, power integrity, channel, and package co-design methodologies, including EM tools like HFSS or EMX.

• Experience mentoring engineers within analog macro design teams.

• Familiarity with mixed-signal validation utilizing high-speed measurement and probing equipment.

🏝️ Benefits

• Flexible work environment.

• Employee-centered culture that prioritizes individual growth, well-being, and a sense of belonging.

• Commitment to diversity, equity, and inclusion.

• Reasonable workplace accommodations for candidates with disabilities.