Senior Manager, ASIC Design Engineering

This is a fully remote position, open to applicants in California.

📋 Description

• Take ownership of ASIC RTL delivery timelines across key milestones by tracking, monitoring, and reporting on progress relative to established plans.

• Leverage data-driven insights to foresee schedule risks and proactively adjust human resources to maintain project timelines.

• Coordinate RTL delivery timelines with DV and emulation readiness while efficiently managing feedback loops and interdependencies.

• Ensure smooth physical design transitions by guaranteeing that design teams deliver high-quality RTL and constraints that reduce timing-closure iterations.

• Monitor physical design feedback and delivery timelines to aid in achieving physical design signoff and tape-out objectives.

• Spearhead long-term headcount planning and organizational structuring for the ASIC department.

• Recognize skill gaps and implement global talent acquisition strategies that align with the product roadmap.

⛳️ Requirements

• Over 15 years of experience in the semiconductor industry, ideally with expertise in high-performance designs on advanced technology nodes, including at least 5 years in a leadership role.

• Bachelor’s or Master’s degree in Computer Engineering, Electrical Engineering, or a related technical field, or equivalent hands-on experience.

• Profound understanding of the collaboration between Design, Verification, Emulation, and Physical Design teams.

• Proven track record of leading extensive engineering teams through multiple complete ASIC product launches in a remote setting.

• Capability to coordinate across various projects, manage risks and escalations, and operate under strict schedules and budget limitations.

• Strong technical knowledge in microarchitecture development, RTL coding (Verilog/System Verilog), synthesis, STA/timing closure, physical design, and verification methodologies.

• Familiarity with one or more industry standards/protocol stacks such as PCIe, Ethernet, UCIe, UALink.

• Demonstrated success in optimizing designs for PPA (power, performance, area) and integrating major subsystems (interconnect, I/O, memory).

🏝️ Benefits

• Competitive compensation package that includes equity, cash, and incentives.

• Health and retirement benefits.

• Generous paid holidays.

• 401(k) with company match.

• Open Time Off (OTO) for regular full-time exempt employees.

• Sick time, bonding leave, and pregnancy disability leave.