Senior Design Verification Engineer

This is a fully remote position, open to applicants in Texas.

📋 Description

• Validate intricate design blocks utilizing similarly complex SV/UVM verification frameworks

• Create and implement pre-silicon verification test strategies

• Formulate directed and random verification tests to ensure block and IP performance

• Design verification components and tools

• Establish verification functional coverage employing industry-standard coverage analysis tools/methodologies

• Troubleshoot regression failures

• Duplicate functional problems identified in external environments or post-silicon; assess and improve tests to confirm bug resolutions

⛳️ Requirements

• A minimum of 8 years of validated verification experience in a hardware development environment

• Robust knowledge of SystemVerilog and UVM verification techniques

• Excellent debugging abilities and familiarity with debugging tools such as DVE/Verdi

• Expertise in Object-Oriented programming, computer architecture, and data structures

• Strong analytical and problem-solving capabilities along with significant attention to detail

• Outstanding interpersonal and communication skills

• Must be adept at collaborating across different geographical locations

🏝️ Benefits

• Health care

• Retirement plan