Senior ASIC Design Engineer

This is a fully remote position, open to applicants in Texas.

📋 Description

• Execute RTL designs utilizing Verilog/System Verilog for high-speed data pathways and packet processing logic.

• Work alongside verification engineers to develop block- and system-level test plans to guarantee thorough design coverage.

• Establish timing constraints for RTL blocks and collaborate with Physical Design engineers to enhance timing closure.

• Assist in post-silicon validation by working with hardware, firmware, and software teams to troubleshoot and resolve ASIC issues.

• Engage in performance optimization and power-efficient design strategies for Host Fabric Interface subsystems.

⛳️ Requirements

• B.S. or M.S. degree in Computer Engineering, Electrical Engineering, or a related discipline.

• Over 8 years of experience in digital design post-college, with expertise in Verilog and System Verilog.

• Background in RTL design for high-speed data pathways or packet processing in ASICs.

• In-depth knowledge of Host Ethernet adapter architectures.

• Acquainted with timing closure and contemporary physical design methodologies.

• Demonstrated capability in system-level debugging and root cause analysis of technical challenges.

• Excellent verbal and written communication skills.

🏝️ Benefits

• Health and retirement benefits.

• Equity, cash, and incentives.

• Medical, dental, and vision coverage.

• Disability and life insurance.

• Dependent care flexible spending account.

• Accidental injury insurance.

• Pet insurance.

• Generous paid holidays.

• 401(k) with company match.

• Open Time Off (OTO).

• Sick time.

• Bonding leave.

• Pregnancy disability leave.