Principal Engineer – STA

This is a fully remote position, open to applicants in India.

📋 Description

• Oversee comprehensive STA and timing signoff processes for full-chip and subsystem-level designs.

• Propel timing closure across setup, hold, signal integrity, noise, crosstalk, IR-aware timing, and MMMC scenarios.

• Establish timing constraints, validate SDCs, and ensure the execution of a robust timing methodology.

• Work in close collaboration with RTL, Physical Design, DFT, CTS, and CAD teams to reach timing convergence.

• Examine and resolve intricate timing violations and critical path hindrances.

• Assist with ECO implementation and signoff verification for advanced node tape-outs.

• Create and enhance automation workflows, scripts, timing dashboards, and methodological improvements.

• Guide engineers and lead technical reviews concerning timing architecture and signoff preparedness.

⛳️ Requirements

• Bachelor’s or Master’s degree in Electronics, Electrical Engineering, VLSI, or a related discipline.

• A minimum of 12 years of experience in STA and timing signoff for ASIC/SOC programs.

• Profound knowledge in setup/hold analysis, timing exceptions, CTS interaction, and timing convergence strategies.

• Practical experience with Synopsys PrimeTime, Tempus, StarRC, and other relevant signoff tools.

• Strong grasp of signal integrity, OCV/AOCV/POCV, CDC, low-power timing methodologies, and effects of advanced nodes.

• Familiarity with advanced technology nodes such as 7nm, 5nm, or smaller.

• Proficient scripting abilities in Tcl, Python, Perl, or Shell scripting.

• Outstanding technical leadership, debugging, communication, and stakeholder management capabilities.

• Good to Have: Experience with package-aware timing analysis and chiplet architectures. Exposure to AI/ML-driven timing optimization strategies. Knowledge of automotive or high-reliability SOC design standards.

🏝️ Benefits

• No Politics, No Bureaucracy

• Remote-Friendly, Global Team

• Move Fast, Ship Real Products