Physical Design Engineer

This is a fully remote position, open to applicants in United States.

📋 Description

• Join the physical design team as an early member.

• Responsible for the physical implementation of intricate blocks and subsystems, from synthesized netlist to signoff.

• Create floorplans that take into account hierarchy, macros, interfaces, congestion, timing, power, and routability.

• Design and enhance power-grid implementations while ensuring IR-drop and electromigration closure.

• Oversee placement, optimization, clock-tree synthesis, routing, extraction, timing closure, and ECO implementation.

• Manage setup, hold, signal-integrity, congestion, and physical implementation challenges.

• Lead timing closure efforts across block boundaries and assist in achieving top-level timing convergence.

• Conduct and facilitate static timing analysis across various modes and corners.

• Assist with signal-integrity analysis and evaluate timing impacts from crosstalk, variation, and physical effects.

• Push for physical signoff, which includes DRC, LVS, antenna checks, density, connectivity, and relevant physical verification prerequisites.

• Conduct or assist with static and dynamic IR-drop and electromigration assessments.

• Formulate implementation strategies for high-performance and physically demanding design segments.

• Collaborate with RTL and architecture teams to pinpoint implementation issues and suggest architectural or logical modifications.

• Work alongside DFT, verification, packaging, SI/PI, and other engineering teams to address cross-functional design challenges.

• Create and refine physical design flows, scripts, automation processes, metrics, and methodologies.

• Assess implementation outcomes and enhance PPA, runtime, convergence, and overall design quality.

• Offer technical guidance and mentorship to physical design engineers.

• Engage in design reviews, methodology assessments, and tapeout readiness evaluations.

• Act as a technical escalation point for complex physical design and signoff challenges.

⛳️ Requirements

• Over 10 years of experience in ASIC or SoC physical design with numerous successful tapeouts.

• Expert knowledge of floorplanning, placement, CTS, routing, optimization, timing closure, ECOs, and physical verification.

• Extensive expertise in static timing analysis and multi-mode, multi-corner timing closure.

• Solid understanding of power delivery, IR drop, electromigration, and signal integrity.

• Proven capability to independently manage complex blocks or significant chip sections through to signoff.

• In-depth understanding of clock design, timing constraints, variation, extraction, and advanced-node physical phenomena.

• Proficient in industry-standard Cadence and/or Synopsys physical implementation and signoff tools.

• Strong scripting and automation abilities with Tcl, Python, Perl, or similar programming languages.

• Skilled in troubleshooting intricate design issues across RTL, timing, physical implementation, and signoff realms.

• Excellent communication skills and the ability to provide technical leadership without formal management authority.

• Experience with advanced process nodes.

• Background in large, high-frequency, or highly interconnected semiconductor designs.

• Familiarity with hierarchical design and top-level physical integration.

• Experience in developing physical design methodologies and automation solutions.

• Collaborative experience with packaging, SI/PI, and power delivery teams.

• Knowledge of multi-die, chiplet, or advanced packaging architectures.

• Familiarity with EDA tool evaluation, benchmarking, and optimization techniques.

• Experience in an early-stage semiconductor environment.

• Capability to independently resolve complex technical issues.

• Comfortable working on both detailed implementation tasks and broader chip-level design considerations.

• Ability to thrive in a highly collaborative, fast-paced engineering organization.

• Must have authorization to work in the United States.

🏝️ Benefits

• Meaningful equity.

• Benefits.

• 401(k).