Lead Signal & Power Integrity Hardware ASIC Simulation Engineer

This is a fully remote position, open to applicants in California.

📋 Description

• Create, document, and execute design guidelines for ultra-high-speed signaling, ensuring that power, performance, and area objectives are met for products.

• Evaluate substrate signal integrity (SI) and power integrity (PI), offering insights and collaborating with the layout team to devise optimal solutions across interposer, substrate, and PCB.

• Design, document, and develop ASIC packages for high-volume, high-quality release, including post-layout extraction and reporting.

• Partner with system collaborators, vendors, and design leads to achieve integrated power and signal integrity while addressing complex technical challenges using advanced technology design rules.

• Establish the processes, methodologies, and tools for designing and implementing intricate ASIC/package developments.

• Lead or engage in chip architecture discussions and define the architecture and design of high-performance ASICs, including reviews of complex IC and analog/mixed-signal circuit designs.

• Guide and support the signal integrity team, junior engineers, and influence packaging/hardware teams, ensuring all technical specifications and innovative solutions are adhered to.

• Foster a culture of design reviews, postmortems, and continuous improvement across multidisciplinary engineering teams.

⛳️ Requirements

• A Bachelor's degree in Electrical Engineering with 8+ years of relevant signal and power integrity experience, or a Master's degree in Electrical Engineering with 6+ years of relevant experience, or a PhD in Electrical Engineering with 3+ years of relevant experience.

• High-Speed Design & Theory: Proficiency in high-speed design principles, including Transmission Line Theory, electromagnetics, scattering parameters, and impedance network analysis, applied to 56G PAM4 SerDes architectures, channel modeling, and BER prediction.

• SI/PI Simulation Proficiency: Familiarity with pre- and post-layout signal and power integrity (SI/PI) simulations utilizing industry-standard EDA tools such as Cadence Sigrity, Ansys HFSS, and Keysight ADS.

• Layout Review & Physical Validation: Experience in conducting thorough layout reviews and physical design validation using tools like Cadence APD and Ansys EM flows to ensure signal performance and mitigate crosstalk.

• Circuit Analysis: Proficient in SPICE for circuit-level analysis, signal modeling, and performance validation.

🏝️ Benefits

• Medical, dental, and vision insurance

• 401(k) plan with a Cisco matching contribution

• Paid parental leave

• Short and long-term disability coverage

• Basic life insurance

• 10 paid holidays per full calendar year

• 1 floating holiday for non-exempt employees

• 1 paid day off for employee’s birthday

• Paid year-end holiday shutdown

• 4 paid days off for personal wellness as determined by Cisco

• 16 days of paid vacation time per full calendar year for non-exempt employees

• Flexible vacation time off program for exempt employees

• 80 hours of sick time off provided on hire date and each January 1st thereafter

• Up to 80 hours of unused sick time carried forward from one calendar year to the next

• Optional 10 paid days per full calendar year to volunteer

• Annual bonuses for non-sales roles