Integrated Circuit Design Verification Engineer

This is a fully remote position, open to applicants in Washington.

📋 Description

• Collaborate within a multi-disciplinary team to design display Integrated Circuits for Augmented Reality.

• Engage closely with digital design, analog logic, software, and verification engineers.

• Develop and implement UVM-based and assertion-driven testbenches.

• Formulate and carry out verification test plans, encompassing functional and code coverage.

• Leverage the Siemens Questa toolset for verification and debugging activities.

• Specify, configure tools, and establish automation processes.

⛳️ Requirements

• Bachelor’s or Master’s degree in Electrical Engineering or equivalent years of experience.

• Over 10 years of experience in ASIC Design Verification.

• In-depth knowledge of UVM and SystemVerilog for sophisticated verification methodologies.

• Proficient understanding of digital functional simulation and tools like Siemens Questa.

• Strong grasp of best practices in Verilog RTL coding.

• Experience with scripting and automation using TCL, Make, Perl, Python, and Shell scripts in a Linux environment.

🏝️ Benefits

• Paid parental leave.

• Comprehensive medical coverage.

• Emotional and mental health support programs.

• Compensation packages that allow you to participate in Snap’s long-term success.