FPGA Developer

This is a fully remote position, open to applicants in Oregon.

📋 Description

• Design, author, and validate synthesizable RTL in SystemVerilog or VHDL for contemporary FPGAs

• Incorporate and configure modulation, demodulation, and packet-switching/routing IP cores

• Develop DSP blocks such as FIR/CIC/polyphase filters, NCOs, mixers, decimation/interpolation chains, channelizers, and demodulation/synchronization logic

• Create simulation testbenches utilizing UVM, cocotb, or similar tools

• Lead functional and code coverage efforts and manage hardware bring-up

• Navigate designs through synthesis, place-and-route, and achieve timing closure

• Examine utilization, congestion, and Fmax challenges and address them at the RTL level

• Integrate ADC/DAC front-ends and mixed-signal interfaces, focusing on clocking, calibration, and lane alignment

• Work collaboratively with systems, firmware, and hardware engineers on defining interfaces and partitioning hardware/software

• Generate design documentation, interface control documents, and verification reports

• Shape technical direction and contribute to the communications architecture for next-generation spacecraft

⛳️ Requirements

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or equivalent experience

• Over 8 years of professional experience in FPGA development using SystemVerilog and/or VHDL

• Proven experience in integrating third-party or vendor IP cores into extensive FPGA designs

• Knowledge of packet-based routing and switching principles, including arbitration, buffering, backpressure, and link-layer framing

• Strong foundational understanding of DSP and hands-on experience with fixed-point HDL signal processing

• Familiarity with high-speed serial transceivers, encompassing 8b/10b or 64b/66b encoding, comma alignment, and lane bonding

• Expertise with the complete Vivado toolchain: synthesis, implementation, timing analysis, and authoring XDC/SDC constraints

• Excellent verification capabilities, including self-checking testbenches, constrained-random stimulus, and coverage-driven methodologies

• Proficient with Git-based workflows and code review practices

• Preferred: Experience with RF and analog front-end technologies

• Preferred: Knowledge of JESD204B/C high-speed converter interfaces

• Preferred: Experience in space, defense, or other high-reliability environments, including radiation-tolerant design practices, TMR, scrubbing, and SEU mitigation

• Preferred: Familiarity with AXI/AXI-Stream interconnect and DMA architecture

• Preferred: Methodologies for clock-domain crossing, formal CDC verification, and hardware bring-up with laboratory instrumentation

🏝️ Benefits

• Competitive salary and performance-based bonuses

• Comprehensive health, dental, and vision insurance

• Retirement savings plan with company matching

• Opportunities for professional development and continuous learning

• Flexible working hours and remote work options