Design Verification Lead

This is a fully remote position, open to applicants in India.

📋 Description

• Define and lead the comprehensive verification architecture for large-scale SoCs, from IP through subsystem to complete SoC level.

• Design and develop reusable, modular, and portable verification platforms across various chip programs.

• Establish methodologies for verification reuse and portability, incorporating Portable Stimulus (PSS)-based flows.

• Oversee the creation of high-performance, coverage-driven testbenches utilizing industry-standard methodologies such as UVM.

• Drive verification strategies at block-level, multi-block/subsystem-level, and full-chip SoC levels.

• Define and uphold verification quality metrics, coverage closure strategies, and sign-off criteria.

• Advocate for a fail-fast philosophy to identify issues early and enhance design quality.

• Propel initiatives toward achieving first-pass silicon success while minimizing escapes and post-silicon debug efforts.

• Utilize AI/ML techniques and AI agents to automate testbench and stimulus generation, boost coverage closure, improve regression and debug productivity, and facilitate intelligent verification QA and anomaly detection.

• Collaborate with design, architecture, physical design, and software teams.

• Mentor and guide design verification teams on best practices, methodology adoption, and architectural decisions.

⛳️ Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.

• Over 10 years of experience in Design Verification, with substantial exposure to large SoC verification.

• Demonstrated experience in defining and implementing verification architectures for complex chips.

• Strong proficiency in SystemVerilog and UVM.

• Extensive expertise in coverage-driven verification, encompassing both functional and code coverage.

• Solid experience in assertion-based verification (SVA).

• Practical experience with Portable Stimulus (PSS) and cross-level stimulus reuse.

• Familiarity with industry-standard protocols such as PCIe, DDR, Ethernet, CXL, and UCIe.

• In-depth understanding of SoC architectures in AI, HPC, or Networking domains.

• Experience addressing multi-IP integration challenges, coherency, high-speed interfaces, and large-scale data movement.

• Strong debugging capabilities and the ability to tackle complex system-level issues.

• Experience with AI/ML applications in verification workflows.

• Exposure to emulation, prototyping, or hybrid verification platforms.

• Knowledge of performance verification and power-aware verification.

• Proven experience in building verification frameworks that are reusable across multiple tape-outs.

• Strong architectural thinking with a systems-level approach.

• High ownership and a quality-first mindset.

• A tendency towards automation, reuse, and scalability.

• Enthusiasm for adopting cutting-edge technologies, particularly AI-driven verification.

• Ability to thrive in a fast-paced environment with a fail-fast, learn-fast mentality.

• Excellent collaboration and leadership abilities.

🏝️ Benefits

• Remote-friendly work environment.

• Opportunity to collaborate with a global team.

• Chance to work on impactful AI/HPC semiconductor infrastructure.

• Engage with paying customers, committed capital, and aggressive timelines.

• Opportunity to build and deliver real silicon products.

• Work alongside experienced founders and teams from a leading semiconductor company.