Design Verification Engineer

This is a fully remote position, open to applicants in Texas.

📋 Description

• Validate intricate design blocks through equally sophisticated SV/UVM verification environments

• Create and implement pre-silicon verification test plans

• Design directed and random verification tests to ensure block and IP functionality

• Construct verification components and tools

• Establish verification functional coverage utilizing industry-standard coverage analysis tools and methods

• Troubleshoot regression failures

• Duplicate functional issues identified in external environments or post-silicon; review and improve tests to confirm bug resolutions

⛳️ Requirements

• Minimum of 3 years of demonstrated verification experience in a hardware development environment

• Strong foundation in SystemVerilog and UVM verification methodologies

• Excellent debugging abilities and familiarity with debugging tools like DVE/Verdi

• Skilled in Object Oriented programming, computer architecture, and data structures

• Strong analytical and problem-solving skills with a keen attention to detail

• Exceptional interpersonal and communication skills

• Must be adept at collaborating across different geographical locations

🏝️ Benefits

• Health care

• Retirement plan benefits