ASIC Packaging Signal/Power Integrity Hardware Engineering Technical Lead

This is a fully remote position, open to applicants in Washington.

📋 Description

• Develop, document, and execute design guidelines for ultra-high-speed signaling.

• Assess substrate signal integrity and power integrity across interposers, substrates, and PCBs.

• Work alongside layout teams to create optimal SI/PI solutions.

• Design, document, and create ASIC packages for high-volume and high-quality releases.

• Conduct post-layout extraction and generate reports.

• Collaborate with system partners, vendors, and design leads to address complex technical challenges.

• Establish processes, methods, and tools for intricate ASIC/package development.

• Lead or engage in chip architecture discussions and the definition, architecture, and design of high-performance ASICs.

• Review complex IC and analog/mixed-signal circuit designs.

• Mentor and assist the signal integrity team and junior engineers.

• Influence packaging and hardware teams to comply with technical specifications.

• Advocate for design reviews, postmortems, and continuous improvement across multidisciplinary engineering teams.

⛳️ Requirements

• Bachelor's degree in Electrical Engineering with 10+ years of relevant experience in signal and power integrity, or a Master's degree in Electrical Engineering with 8+ years of experience, or a PhD in Electrical Engineering with 4+ years of relevant experience.

• Proficiency in high-speed design principles, including Transmission Line Theory, electromagnetics, scattering parameters, and impedance network analysis.

• Experience in applying high-speed design principles to 56G PAM4 SerDes architectures, channel modeling, and BER prediction.

• Familiarity with pre- and post-layout SI/PI simulations.

• Competence with industry-standard EDA tools such as Cadence Sigrity, Ansys HFSS, and Keysight ADS.

• Experience in conducting detailed layout reviews and validating physical designs.

• Knowledge of Cadence APD and Ansys EM flows.

• Working understanding of SPICE for circuit-level analysis, signal modeling, and performance validation.

• Preferred: Ability to communicate technical concepts to a diverse audience.

• Preferred: Experience with HBM or high-speed memory interface SI.

• Preferred: Experience with UCIe or proprietary die-to-die interfaces.

• Preferred: Experience with advanced packaging such as CoWoS, EMIB, and interposer-based designs.

• Preferred: Working knowledge of Vector Network Analysis.

• Preferred: Basic understanding of IBIS.

🏝️ Benefits

• Medical, dental, and vision insurance.

• 401(k) plan with a Cisco matching contribution.

• Paid parental leave.

• Short- and long-term disability coverage.

• Basic life insurance.

• Cisco restricted stock unit grants, subject to eligibility and continued employment.

• 10 paid holidays per full calendar year.

• 1 floating holiday for non-exempt employees.

• 1 paid day off for the employee’s birthday.

• Paid year-end holiday shutdown.

• 4 paid days off for personal wellness.

• 16 days of paid vacation per full calendar year for non-exempt employees.

• Flexible vacation time-off program with no defined limit for eligible exempt employees.

• 80 hours of sick time off provided on hire date and each January 1st thereafter.

• Up to 80 hours of unused sick time carried forward.

• Additional paid time off for critical or emergency family issues.

• Optional 10 paid volunteer days per full calendar year.

• Annual bonuses for non-sales roles, subject to Cisco’s policies.