ASIC Packaging Signal/Power Integrity Hardware Engineering Technical Lead

This is a fully remote position, open to applicants in California, +3 more states.

📋 Description

• Develop, document, and implement design guidelines for ultra-high-speed signaling

• Analyze substrate signal integrity and power integrity

• Collaborate with layout teams to find solutions across interposer, substrate, and PCB

• Design, document, and create ASIC packages for high-volume, high-quality production

• Conduct post-layout extraction and reporting

• Work alongside system partners, vendors, and design leads to address complex technical challenges

• Establish processes, methodologies, and tools for intricate ASIC/package development

• Lead or engage in discussions regarding chip architecture and high-performance ASIC design

• Review complex IC and analog/mixed-signal circuit designs

• Guide the signal integrity team and junior engineers

• Influence packaging and hardware teams to adhere to technical specifications

• Advocate for design reviews, postmortems, and ongoing improvement across engineering teams

⛳️ Requirements

• Bachelor’s degree in Electrical Engineering with 10+ years of relevant signal and power integrity experience, or a Master’s degree with 8+ years, or a PhD with 4+ years

• Proficiency in Transmission Line Theory, electromagnetics, scattering parameters, and impedance network analysis

• Experience in applying high-speed design principles to 56G PAM4 SerDes architectures, channel modeling, and BER prediction

• Familiarity with pre- and post-layout SI/PI simulations

• Proficient in industry-standard EDA tools such as Cadence Sigrity, Ansys HFSS, and Keysight ADS

• Experience in conducting layout reviews and validating physical design using Cadence APD and Ansys EM flows

• Working knowledge of SPICE

• Ability to clearly communicate technical concepts to various audiences, both verbally and in writing

• Experience with HBM or high-speed memory interface signal integrity

• Familiarity with die-to-die interfaces like UCIe or proprietary interfaces

• Experience with advanced packaging solutions such as CoWoS, EMIB, and interposer-based designs

• Basic understanding of Vector Network Analysis

• Fundamental knowledge of IBIS

🏝️ Benefits

• Medical, dental, and vision insurance

• 401(k) plan with a Cisco matching contribution

• Paid parental leave

• Short- and long-term disability coverage

• Basic life insurance

• Cisco restricted stock unit grants may be available

• 10 paid holidays per full calendar year

• 1 floating holiday for non-exempt employees

• 1 paid day off for the employee’s birthday

• Paid year-end holiday shutdown

• 4 paid days off for personal wellness

• 16 days of paid vacation time per full calendar year for non-exempt employees

• Flexible vacation time off program with no defined limit for eligible exempt employees

• 80 hours of sick time off provided on the hire date and each January 1st thereafter

• Up to 80 hours of unused sick time can be carried forward

• Additional paid time off for critical or emergency family matters

• Optional 10 paid volunteer days per full calendar year

• Annual bonuses for non-sales roles, subject to Cisco policies