Senior/Lead ASIC Engineer

This is a fully remote position, open to applicants in Peru.

📋 Description

• Lead the architecture, implementation, and sign-off of DFT.

• Spearhead the insertion of scan, scan chains, and compression workflows.

• Take ownership of MBIST/LBIST integration and debugging processes.

• Conduct silicon debugging, perform failure analysis, and determine root causes.

• Create DFT constraints (SDC) and conduct timing analysis.

• Assist in the generation of ATPG, simulation, and coverage closure.

• Work with JTAG, boundary scan, and iJTAG technologies.

• Collaborate with RTL, PD, STA, and validation teams.

• Mentor and guide junior engineers.

• Develop automation scripts using TCL, Perl, or Python.

⛳️ Requirements

• Over 10 years of hands-on experience in ASIC DFT.

• Strong foundational knowledge of DFT principles and fault models.

• Expertise in scan, ATPG, MBIST, JTAG, and debugging techniques.

• Proficient in using Synopsys, Cadence, and Siemens tools.

• Experience in post-silicon validation.

• Exposure to large SoC and hierarchical DFT implementations.

🏝️ Benefits

• Competitive salary and performance-based bonuses.

• Comprehensive health, dental, and vision insurance.

• Opportunities for professional development and continuous learning.

• Flexible work hours and remote work options.

• Collaborative and innovative work environment.