Senior System-on-Chip Design Engineer

This is a fully remote position, open to applicants in India.

📋 Description

• Design and implement SoC RTL, including integration and associated RTL design checks.

• Engage in and contribute to architectural discussions.

• Collaborate with DFT, Verification, and Physical Design teams.

• Take ownership of specific parts of the SoC design, which may include one or more subsystems and full-chip-level design tasks.

• Schedule deliverables in accordance with overall project timelines.

• Execute design, frontend, DFT, and verification tasks throughout all phases.

• Manage chip-level clocking, boot processes, and low-power design aspects.

• Perform PPA analysis and evaluate/select IP components.

• Work in partnership with global teams.

• Collaborate with design leads and architects while adhering to established best practices.

• Contribute to SoC design integration and quality assessment activities.

• Take responsibility for PPA, design constraints, and Lint/CDC tasks as relevant.

• Coordinate with verification, physical design, DFT, and other teams to ensure the production of high-quality silicon.

• Mentor and train new engineers.

• Foster collaboration with R&D team members and leads across Architecture, SoC, and Implementation.

• Influence technical strategy and drive innovation in products, technology, and/or patents.

• May engage in ASIC implementation tasks such as synthesis, timing constraints, ECOs, STA, power intent implementation and validation, lint, power analysis, and CDC/RDC analysis and validation.

• May participate in RTL development and physical design activities from floor-plan definition through place and route.

• Model and analyze performance, area, power, and system cost trade-offs for various micro-architectures.

⛳️ Requirements

• BTech/MTech/PhD with over 10 years of experience in the semiconductor sector.

• Proven team leader or technical manager with a track record of leading teams in SoC Design and Verification.

• Experience with wireless standards and connectivity, including signal processing.

• Familiarity with SoCs utilizing ARM Core Architecture, RISC V, Power PC, etc.

• Understanding of high-speed peripherals such as DDR, PCIe, ENET, and UCIe.

• Knowledge of interfaces including QSPI, I2C, and USB.

• Expertise in memory subsystem architecture.

• Familiarity with Neural Accelerators, CPUs, ARM subsystems, and AXI/APB interfaces.

• Strong domain expertise in clocking, system modes, power management, debugging, interconnects, security, and other architectural elements.

• Experience with Lint, CDC, RDC, and Power Aware/Low power design methodologies.

• Understanding of power management concepts.

• Commitment to continuous learning and improvement.

• Desire to push the boundaries of technology.

• Knowledge and understanding of chiplet implementations and System In Package (SiP) concepts.

• Familiarity with the latest packaging and substrate technologies.

• Knowledge of Die to Die interfaces.

🏝️ Benefits

• Competitive compensation package.

• Comprehensive paid time off, including vacations and sick leave.

• Opportunity to join a well-funded, fabless AI semiconductor startup.

• Chance to contribute to the growth and success of a company that is revolutionizing the AI software and hardware co-design landscape.