Senior Mixed-Signal Verification Engineer

This is a fully remote position, open to applicants in United States.

📋 Description

• Design advanced behavioral models for analog and mixed-signal intellectual property (including ADCs, DACs, PLLs, LDOs, RF front-end blocks, biasing, amplifiers, etc.)

• Generate abstracted models utilizing Verilog, Verilog-AMS, or SystemVerilog

• Establish regression infrastructure and mixed-signal testbenches to facilitate co-simulation (digital + analog)

• Incorporate AMS models into digital verification frameworks (UVM-based)

• Determine and construct the mixed-signal verification methodology for top-level SoC and subsystem validation

• Assist in architectural exploration via early-phase modeling and system-level simulations

• Collaborate with analog/RF designers to capture real-world analog behaviors and translate them into precise behavioral abstractions

• Partner with digital and verification teams to guarantee the smooth integration of AMS models

• Offer modeling and verification expertise during architectural assessments, PDR/CDR, and silicon bring-up

• Serve as a technical leader and subject-matter expert.

⛳️ Requirements

• M.S. or Ph.D. in Electrical Engineering, Computer Engineering, or a related discipline

• Over 5 years of experience in analog/mixed-signal modeling and/or AMS verification

• Practical experience with SystemVerilog, Verilog-AMS, wreal/RNM, or similar modeling languages

• In-depth knowledge of analog/mixed-signal circuits (including PLLs, LDOs, ADC/DACs, RF/IF paths, clocking, amplifiers)

• Familiarity with mixed-signal co-simulation platforms (Cadence AMS Designer, Synopsys VCS AMS, or comparable tools)

🏝️ Benefits

• Comprehensive benefits package, including paid time off

• Medical, dental, and vision coverage

• Life insurance

• Paid parental leave

• Numerous additional perks