Senior Manager, ASIC Design Engineering

This is a fully remote position, open to applicants in California.

📋 Description

• Lead and develop the RTL design engineering team.

• Report directly to the VP of ASIC Engineering while collaborating with executive leadership.

• Oversee a team of design engineers.

• Spearhead the full-lifecycle development of next-generation, high-performance networking ASICs.

• Establish and manage RTL implementation schedules across all SoC subsystems and full-chip milestones.

• Leverage hands-on ASIC RTL design implementation expertise, methodologies, and SoC flows, from microarchitecture definition to RTL delivery and tape-out readiness.

• Coordinate cross-functional execution with Architecture, Design Verification, Emulation, and Physical Design teams.

• Own ASIC RTL delivery schedules by tracking, monitoring, and reporting progress against established plans.

• Utilize data-driven insights to anticipate schedule risks and proactively reallocate human resources as needed.

• Align RTL delivery schedules with Design Verification and emulation enablement efforts.

• Manage feedback loops and dependencies effectively.

• Facilitate high-quality RTL and constraints during physical design handoffs.

• Monitor physical design feedback and delivery schedules to ensure support for physical design signoff and tape-out milestones.

• Lead long-term headcount planning and organizational design for the ASIC department.

• Identify skill gaps and implement global talent acquisition strategies that support the product roadmap.

• Build a nimble, efficient, world-class design team.

⛳️ Requirements

• 15+ years of experience in the semiconductor industry, preferably with high-performance designs on advanced technology nodes.

• A minimum of 5 years in people management.

• B.S. or M.S. in Computer Engineering, Electrical Engineering, or a related technical field, or equivalent practical experience.

• Profound understanding of the interactions among Design, Verification, Emulation, and Physical Design teams.

• Proven track record of leading large engineering organizations through multiple full-cycle ASIC product launches in a remote environment.

• Ability to coordinate across multiple projects, manage risks and escalations, and operate under tight schedules and budget constraints.

• Strong technical knowledge in microarchitecture development, RTL coding (Verilog/System Verilog), synthesis, STA/timing closure, physical design, and verification methodologies.

• Familiarity with one or more industry standards/protocol stacks such as PCIe, Ethernet, UCIe, UALink.

• Demonstrated capability to optimize designs for PPA (power, performance, area) and integrate major subsystems (interconnect, I/O, memory).

• Preferred: Experience with AI-based design implementation and verification flows, scripting for automation, milestone tracking, and flow integration.

• Preferred: Background in building globally distributed ASIC design teams and scaling engineering practices in a remote setting.

🏝️ Benefits

• Equity, cash, and incentives.

• Health benefits.

• Retirement benefits.

• Medical coverage.

• Dental coverage.

• Vision coverage.

• Disability insurance.

• Life insurance.

• Dependent care flexible spending account.

• Accidental injury insurance.

• Pet insurance.

• Generous paid holidays.

• 401(k) with company match.

• Open Time Off (OTO) for regular full-time exempt employees.

• Sick time.

• Bonding leave.

• Pregnancy disability leave.

• Dynamic, flexible work environment.

• Performance-based incentives, including an annual bonus or sales incentives (depending on the role).