Senior Formal Verification Engineer – Vector Unit

This is a fully remote position, open to applicants in Texas.

📋 Description

• Create, implement, and sustain effective formal verification environments for intricate Vector Unit sub-blocks.

• Utilize advanced word-level modeling, bit-blasting, and algebraic rewriting techniques.

• Independently identify and rectify proof-convergence issues, over-constraints, and state-space explosions.

• Establish formal environments to mathematically validate adherence to the RISC-V Vector Extension specification.

• Work closely with simulation engineers to maximize bug detection efficiency.

⛳️ Requirements

• B.S./M.S. in Computer Engineering, Electrical Engineering, or Computer Science; or a Ph.D. in formal methods or computer arithmetic.

• 5+ years of experience in production-grade hardware verification (or Ph.D. + 1–3 years).

• Strong expertise in arithmetic formal verification, algebraic rewriting, and word-level modeling.

• Solid understanding of high-width execution pipelines, vector execution units, or floating-point/integer arithmetic hardware.

• Proficient in commercial EDA formal tools (e.g., Cadence JasperGold/DPV, Synopsys VC Formal, Siemens OneSpin).

• Fluent in SystemVerilog and SVA; skilled in scripting (Python, Tcl, or Bash).

🏝️ Benefits

• Opportunities for professional growth and development.

• Flexible working arrangements.