Senior Formal Verification Engineer

This is a fully remote position, open to applicants in Colorado, +3 more states.

📋 Description

• Validating sophisticated AI-related ASIC builds and features through advanced formal verification techniques.

• Working closely with architecture and RTL teams to define properties and address intricate issues.

• Implementing formal verification to rigorously confirm that critical build properties are in alignment with specifications.

• Communicating formal verification coverage to stakeholders.

• Creating advanced formal verification environments and methodologies for intricate ASIC designs.

• Assisting with silicon bring-up and debugging using formal methods as applicable.

⛳️ Requirements

• BS/MS/PhD or equivalent experience in Computer Science, Computer Engineering, or Electrical Engineering.

• Over 5 years of experience in ASIC verification, with at least 3 years dedicated to formal verification techniques.

• Expertise in SystemVerilog Assertions (SVA) and formal property verification.

• Familiarity with at least one leading formal verification tool in the industry (such as JasperGold, VC Formal, etc.).

• Exceptional ability to leverage AI tools in day-to-day engineering tasks to effectively resolve challenges.

• Strong written and verbal communication skills.

• Meticulous attention to detail.

🏝️ Benefits

• Competitive salaries.

• Comprehensive benefits package.

• Equity opportunities.