Senior DFT Engineer

This is a fully remote position, open to applicants in United States.

📋 Description

• Establish and execute DFT architecture for mixed-signal SoCs, encompassing scan, MBIST, LBIST, and boundary scan methodologies.

• Spearhead RTL-level DFT insertion, scan chain implementation and optimization, test point integration, and low-power DFT techniques.

• Manage the development and execution of ATPG flows by producing high-quality stuck-at, transition, and path delay test patterns. Lead efforts in coverage closure, pattern optimization, and debugging pattern failures alongside silicon correlation.

• Design and implement DFT strategies for mixed-signal components, including wrapper-based solutions and analog test interfaces with BIST methodologies.

• Collaborate with RTL, DV, and PD teams to guarantee seamless DFT integration at both RTL and gate-level, ensuring alignment of timing and physical constraints (such as scan reordering and compression).

• Oversee DFT verification and signoff processes, which include analyzing Scan/ATPG coverage metrics, conducting DRC/Lint checks (for DFT rule compliance), and performing gate-level simulations along with pattern validation.

• Assist in the bring-up and silicon debugging efforts by evaluating tester failures, yield challenges, and ATPG pattern correlation with silicon performance.

• Contribute to the enhancement of methodologies, automation, and flow optimizations.

⛳️ Requirements

• B.S. or M.S. degree in Electrical Engineering or a related discipline.

• Over 7 years of experience in DFT for intricate SoCs.

• Substantial hands-on experience with RTL DFT insertion (including scan, compression, and test points) along with ATPG tools and workflows.

• Profound knowledge of scan architectures, compression methodologies, fault models (such as stuck-at, transition, bridging, and path delay), as well as coverage analysis and closure techniques.

• Familiarity with low-power DFT methodologies.

• Understanding of mixed-signal integration challenges and testing strategies.

• Exceptional debugging capabilities across RTL, gate-level, and silicon domains.

🏝️ Benefits

• Comprehensive benefits package including paid time off.

• Medical, dental, and vision coverage.

• Life insurance.

• Paid parental leave.

• Numerous additional perks.