Senior ASIC Emulation Engineer

This is a fully remote position, open to applicants in United States.

📋 Description

• Spearhead the bring-up, deployment, and enhancement of pre-silicon emulation platforms.

• Construct, integrate, and sustain full-chip, multi-chip, and system-level emulation models utilizing Palladium, ZeBu, or Veloce.

• Establish and refine emulation strategies, methodologies, and workflows throughout the ASIC organization.

• Compile, map, and enhance RTL designs for improved emulation performance, capacity, and stability.

• Create and integrate transactors, BFMs, speed adapters, and virtualization interfaces.

• Assist in system-level hardware/software integration, complex use-case validation, and representative end-to-end workloads.

• Aid the DV team in executing targeted, high-value emulation tests and optimizing workflows to alleviate simulation bottlenecks.

• Equip firmware, bootloader, driver, and software teams with emulation platforms and HW/SW integration debugging support.

• Execute emulation workloads, troubleshoot failures, conduct root-cause analysis, and resolve issues with design and verification teams.

• Sustain and enhance automation for compile flows, regression management, and continuous integration.

• Engage in architecture reviews and microarchitecture discussions to influence design-for-emulation practices.

• Assist in silicon bring-up and post-silicon validation through test reuse, diagnostics, and pre/post-silicon correlation.

• Oversee interactions with external IP providers or emulation partners as necessary.

• Collaborate with architecture, RTL design, DFT, DV, firmware, physical design, and silicon validation teams.

⛳️ Requirements

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related discipline.

• Over 5 years of experience in ASIC/SoC development with a focus on emulation.

• Strong grasp of SystemVerilog, digital logic, RTL flows, DV methodologies, and ASIC development lifecycles.

• Practical experience with Palladium, ZeBu, or Veloce, including model building, debugging, and performance optimization.

• Proficient in Python, Perl, and TCL for automation and tooling purposes.

• Background in hardware/software interfaces, embedded processors, firmware bring-up, and C/C++-based system-level testing.

• Knowledge of APB, AHB, AXI, JTAG, and SPI buses and protocols.

• Experience in cross-functional debugging involving RTL, DV, firmware, physical design, and validation teams.

• Understanding of pre- and post-silicon debugging methodologies and correlation workflows.

• Must be a U.S. Person as defined by ITAR or otherwise eligible for a federally issued export-control license.

• Preferred: experience with FPGA prototyping platforms, low-power modes and power-aware emulation, analog/mixed-signal behavioral models, SERDES, PCIe, Ethernet, USB, or multi-gigabit PHYs.

🏝️ Benefits

• Equity in the company

• Comprehensive benefits package

• Paid time off

• Medical coverage

• Dental coverage

• Vision coverage

• Life insurance

• Paid parental leave

• Other perks

• Reasonable accommodation during employment application or interviews