Senior ASIC Design Verification Engineer

This is a fully remote position, open to applicants in United States.

📋 Description

• Validate the functionality, performance, and reliability of custom silicon designs.

• Establish the verification strategy and contribute to the verification methodology.

• Create and implement verification plans at the block level, subsystem level, and full-chip level.

• Construct SystemVerilog/UVM test benches, including agents, monitors, scoreboards, checkers, and coverage models.

• Develop SystemVerilog Assertions and incorporate formal verification when necessary.

• Lead constrained-random and directed testing approaches for functionality, edge cases, and stress testing.

• Conduct simulations, analyze failures, perform root cause analysis, and work with RTL designers to resolve issues.

• Implement and sustain functional, code, and assertion coverage, ensuring coverage closure for sign-off.

• Oversee regression testing, simulation farms, and continuous integration pipelines.

• Engage in design reviews, microarchitecture discussions, and advocate for design-for-verification best practices.

• Collaborate with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers.

• Assist in silicon bring-up and post-silicon validation through test reuse, diagnostic efforts, and debug analysis.

• Participate in interviews for the ASIC team.

• Enhance design verification methodologies and propose improvements.

• Interact with external IP providers and verification partners as necessary.

⛳️ Requirements

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related discipline.

• Over 5 years of experience in ASIC/SoC verification.

• Strong understanding of SystemVerilog, digital logic, RTL design, and hardware verification processes.

• Proficient with simulation tools such as VCS, Xcelium, or Questa.

• Skilled in waveform debugging tools such as Verdi or SimVision.

• Experienced with coverage tools.

• Knowledgeable in scripting languages like Python, Perl, or TCL.

• Familiar with test planning, UVM-based testbench development, constrained-random testing, functional coverage, and SystemVerilog assertions.

• Experienced in regression management, coverage analysis, version control (Git), and CI/CD automation.

• Understanding of industry-standard interfaces such as APB, AHB, or AXI.

• Familiarity with embedded processor designs and firmware/bare metal coding in C or C++.

• Must qualify as a “U.S. person” as defined by ITAR or be eligible for a federally issued export control license.

• Nice-to-have: Experience in developing and integrating reference models.

• Nice-to-have: Knowledge of low power verification techniques.

• Nice-to-have: Familiarity with gate-level simulation and analog behavioral models.

• Nice-to-have: Experience in post-silicon validation planning and execution.

• Nice-to-have: Experience working in cross-functional, geographically distributed teams.

• Experience in space, telecom, or RF/digital mixed systems is an advantage.

🏝️ Benefits

• Equity in the company

• Paid time off

• Medical coverage

• Dental coverage

• Vision coverage

• Life insurance

• Paid parental leave

• Numerous other perks

• Reasonable accommodations for employment applications or interviews