Principal ASIC Design Verification Engineer

This is a fully remote position, open to applicants in United States.

📋 Description

• Validate the functionality, performance, and reliability of custom silicon designs.

• Establish the verification strategy and contribute to the development of verification methodologies.

• Create and implement verification plans for block-level, subsystem-level, and full-chip environments.

• Construct SystemVerilog/UVM test benches that include agents, monitors, scoreboards, checkers, and coverage models.

• Develop SystemVerilog Assertions and incorporate formal verification as necessary.

• Lead constrained-random and directed testing approaches targeting functionality, edge cases, and stress scenarios.

• Execute simulations, analyze failures, conduct root-cause investigations, and work alongside RTL designers to resolve issues.

• Implement and uphold functional, code, and assertion coverage while ensuring coverage closure for sign-off.

• Oversee regression testing, simulation farms, and CI pipelines.

• Engage in design reviews, microarchitecture discussions, and promote design-for-verification best practices.

• Collaborate with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers.

• Assist with silicon bring-up and post-silicon validation through test reuse, diagnostics, and debugging analysis.

• Take part in ASIC team interviews.

• Promote advancements in DV methodologies and enhancements.

• Manage external IP providers and verification partners as required.

• Lead significant and/or intricate systems.

• Contribute to developing first-generation silicon at K2 Space, which manufactures high-power satellites for commercial and U.S. government clients.

⛳️ Requirements

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related discipline.

• Over 10 years of experience in ASIC/SoC verification.

• Strong grasp of SystemVerilog, digital logic, RTL design, DFT, and hardware design and verification processes.

• Expertise in simulation tools such as VCS, Xcelium, and Questa.

• Proficient in waveform debugging tools like Verdi and SimVision.

• Skilled in coverage tools and scripting languages, including Python, Perl, and TCL.

• Familiarity with test planning, UVM-based testbench development, constrained-random testing, functional coverage, and SystemVerilog assertions.

• Experience with regression management, coverage analysis, version control systems like Git, CI/CD automation, and gate-level simulation.

• Background in developing and integrating reference models.

• Experience with embedded processor-based designs and firmware/bare metal programming in C and C++.

• Knowledge of industry-standard interfaces such as APB, AHB, and AXI.

• Participation in post-silicon validation planning and execution.

• The selected candidate must be a U.S. person as defined by ITAR or otherwise eligible for a federally issued export control license.

• Experience with low power verification, analog behavioral models, physical design processes, working with geographically distributed teams, and space, telecom, or RF/digital mixed systems is considered a plus.

🏝️ Benefits

• Equity in the company.

• Paid time off.

• Medical, dental, and vision coverage.

• Life insurance.

• Paid parental leave.

• Comprehensive benefits package.

• Numerous additional perks.

• Reasonable accommodation for employment applications or interviews.