This is a fully remote position, open to applicants in Ukraine.

📋 Description

• Comprehend the design requirements, microarchitecture, and system architecture of the team's intellectual property (IP) and system solutions.

• Work in conjunction with design and verification engineers to grasp features and support needs.

• Develop crucial functional blocks that adhere to design and architectural specifications utilizing Verilog.

• Troubleshoot test failures to identify the root cause.

• Collaborate with verification and emulation engineers to address design defects and rectify design issues.

⛳️ Requirements

• B.E/M.E/M.Tech or B.S/M.S in Electrical Engineering (EE) or Electronics and Communication Engineering (ECE) with over 10 years of relevant experience in IP design.

• Familiarity with Ethernet protocols and IEEE 802.3 standards, including MAC/PCS/PMA, PTP (IEEE 1588), pause/flow control, and FEC for speeds ranging from 10GE to 100GE and beyond.

• Domain expertise in AXI streaming, AXI4-Lite, and other connectivity protocols.

• Experience in achieving timing closure for complex designs.

• Skilled in debugging firmware and RTL code using simulation tools.

• Knowledge of ASIC flow tools such as Primetime and Design Compiler, along with code coverage and LINT, is a beneficial addition.

• Strong working knowledge of SystemVerilog.

• Proficiency in scripting languages like Perl and Python.

• Self-motivated, driven, and results-oriented.

• Exceptional interpersonal, written, group communication, and problem-solving abilities.

• Strong organizational and execution skills, with the ability to multitask, prioritize, and meet deadlines while delivering high-quality results.