Principal EDA R&D Engineer

This is a fully remote position, open to applicants in California, +3 more states.

📋 Description

• Oversee the research, architecture, and development of foundational formal verification engines enhanced by Agentic AI frameworks.

• Design, create, and enhance formal verification algorithms such as Model Checking, SAT/SMT solvers, BDDs, Equivalence Checking, and Theorem Proving.

• Create, develop, and implement multi-agent AI systems utilizing LLMs, Reinforcement Learning, and Graph Neural Networks.

• Construct AI systems that evaluate RTL topologies, segment extensive design spaces, and adaptively optimize solver parameters.

• Establish orchestration layers that enable autonomous AI agents to collaborate on handling multi-billion-gate builds with significant sequential depth.

• Create engines for the ingestion, abstraction, and automatic generation of intricate System Verilog Assertions derived from natural language specifications and architectural intent.

• Propel features from algorithmic research through to implementation in high-performance C/C++ environments.

• Guarantee smooth integration into commercial EDA tool suites.

⛳️ Requirements

• Ph.D. or Master’s degree, or equivalent experience, in Computer Science, Electrical Engineering, Computer Engineering, or a related quantitative discipline.

• At least 15 years of professional R&D experience specifically focused on developing commercial or advanced academic Electronic Design Automation (EDA) hardware verification tools.

• Profound mathematical knowledge and practical expertise in formal methods, including bounded model checking (BMC), unbounded model checking (PDR/IC3), abstract interpretation, and theorem proving.

• Expert-level skills in C/C++ (Modern C++17/20), with a focus on high-performance data structures, memory optimization, and multi-threading.

• Demonstrated experience in building or researching Agentic AI pipelines, multi-agent frameworks like LangChain, AutoGen, or CrewAI, tool-use execution, and prompt-engineering designed for structured code or hardware descriptions.

• Familiarity with RTL languages such as System Verilog, VHDL, and Verilog.

• Strong understanding of System Verilog Assertions (SVA).

🏝️ Benefits

• Equity

• Benefits