Principal ASIC Design Verification Engineer

This is a fully remote position, open to applicants in United States.

📋 Description

• Validate the functionality, performance, and robustness of custom silicon designs.

• Establish the verification strategy and contribute to the overall methodology.

• Create and implement verification plans for block-level, subsystem-level, and full-chip environments.

• Construct SystemVerilog/UVM test benches, which include agents, monitors, scoreboards, checkers, and coverage models.

• Develop SystemVerilog Assertions (SVA) and incorporate formal verification as necessary.

• Lead constrained-random and directed testing approaches to verify functionality, edge cases, and stress scenarios.

• Execute simulations, diagnose failures, conduct root-cause analysis, and collaborate with RTL designers to address issues.

• Implement and uphold functional coverage, code coverage, assertion coverage, and ensure coverage closure for sign-off.

• Oversee regression testing, simulation farms, and CI pipelines to maintain high test throughput and expedite debugging iterations.

• Engage in design reviews, microarchitecture discussions, and promote design-for-verification (DFV) best practices.

• Collaborate extensively with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers to guarantee comprehensive coverage and testing.

• Assist in silicon bring-up and post-silicon validation through test reuse, diagnostics, and debugging analysis.

• Take part in ASIC team interviews.

• Propel the advancement of DV methodologies and enhancements.

• Manage external IP providers and verification partners as required.

• Lead initiatives on large and/or complex systems.

⛳️ Requirements

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related discipline.

• 10+ years of experience in ASIC/SoC verification.

• Strong understanding of SystemVerilog, digital logic, RTL design, DFT, and hardware design and verification processes.

• Expertise with various simulation tools (VCS, Xcelium, Questa), waveform debugging tools (Verdi, SimVision), coverage tools, and scripting languages (e.g., Python, Perl, TCL).

• Experience in test planning, UVM-based testbench development, constrained-random testing, functional coverage, and SystemVerilog assertions.

• Background in regression management, coverage analysis, version control (e.g., Git), CI/CD automation, and gate-level simulation.

• Familiarity with developing and integrating reference models.

• Experience with embedded processor-based designs and firmware/bare metal coding (e.g., C, C++).

• Knowledge of various industry-standard interfaces (e.g., APB/AHB/AXI).

• Participation in post-silicon validation planning and execution.

🏝️ Benefits

• Comprehensive benefits package including paid time off

• Medical/dental/vision coverage

• Life insurance

• Paid parental leave

• Other perks