High-Speed Analog Layout Engineer

This is a fully remote position, open to applicants in Texas.

📋 Description

• Develop physical silicon layouts for high-speed or high-frequency mixed-signal circuits, such as SerDes, ADCs, DACs, PLLs, and high-speed blocks.

• Formulate block-level and chip-top-level floor plans.

• Oversee the integration of hierarchical blocks.

• Manage micro-bump or package-aware co-design.

• Tackle layout-dependent effects, device matching, common-centroid structures, guard rings, isolation, and shielding.

• Ensure compliance with DRC, LVS, ERC, antenna rules, as well as EM/IR reliability and ESD protection.

⛳️ Requirements

• Must possess experience with TSMC 4NM technology.

• Typically, 5 to 12+ years of practical custom IC layout experience is required.

• Familiarity with deep sub-micron or advanced CMOS/FinFET nodes is essential.

• Experience with advanced nodes such as TSMC N3, N5, or N7 is necessary.

• Proficiency at lower nodes (N3, N5) is crucial.

• Background in designing physical silicon layouts for high-speed or high-frequency mixed-signal circuits is needed.

• Understanding of floor planning and hierarchical block integration is required.

• Experience in micro-bump or package-aware co-design is advantageous.

• Knowledge of layout-dependent effects (LOD, WPE, LDE) is important.

• Expertise in device matching and common-centroid structures is expected.

• Experience with guard rings, isolation, and shielding, including coaxial, differential, and ground shields is necessary.

• Proven experience in closing DRC, LVS, ERC, antenna rules, EM/IR reliability, and ESD protection is required.

🏝️ Benefits

• Contract engagement for a duration of 6–12 months.