DFT Architect

This is a fully remote position, open to applicants in India.

📋 Description

• Establish and manage the SOC-level Design for Test (DFT) architecture and testing strategy for intricate semiconductor designs.

• Spearhead the implementation of scan insertion, Automatic Test Pattern Generation (ATPG), Memory Built-In Self-Test (MBIST), Logic Built-In Self-Test (LBIST), boundary scan, and test compression techniques.

• Lead DFT planning and integration in accordance with objectives related to power, timing, area, and test coverage.

• Collaborate with RTL, Physical Design, Verification, and Product Engineering teams to ensure smooth DFT integration and final approval.

• Evaluate and address DFT-related timing, routing, and testability issues.

• Assist in silicon bring-up, debugging, diagnosis, yield analysis, and the optimization of production testing.

• Create and improve DFT automation processes, methodologies, and reusable frameworks.

• Guide junior engineers and offer technical leadership across various projects.

⛳️ Requirements

• Bachelor’s or Master’s degree in Electronics, Electrical Engineering, VLSI, or a related discipline.

• Over 10 years of experience in ASIC/SOC DFT implementation and architecture.

• Profound knowledge in scan, ATPG, MBIST, JTAG, compression, and low-power DFT methodologies.

• Practical experience with recognized DFT tools such as Siemens Tessent, Synopsys DFT Compiler/TestMAX, or similar tools.

• Strong comprehension of RTL design, timing, physical design limitations, and silicon debugging.

• Experience with advanced technology nodes and extensive SOC integration.

• Proficient in scripting and automation using Tcl, Python, Perl, or Shell.

• Outstanding leadership, problem-solving abilities, and skills in cross-functional collaboration.

🏝️ Benefits

• Remote-Friendly, Global Team

• Ownership mindset

• Bias for action

• Deep technical expertise

• Low ego, high standards