ASIC Physical Design Lead

This is a fully remote position, open to applicants in United States.

📋 Description

• Oversee and manage all physical design processes from RTL handoff, floorplanning, and place and route to final GDSII delivery.

• Establish execution strategies, timelines, design methodologies, and quality checkpoints for the complete physical design workflow.

• Design and implement floorplanning strategies for large, hierarchical System on Chips (SoCs).

• Integrate Intellectual Properties (IPs) and macros, define physical partitions and hierarchy, and create power grid and clock distribution topologies.

• Collaborate with Architecture and RTL teams to assess physical feasibility, readiness for timing closure, and targets for area and power.

• Lead block-level and top-level place and route utilizing industry-standard EDA tools.

• Propel timing convergence across various corners, modes, voltage domains, and operating conditions.

• Manage PPA optimization, congestion alleviation, and physical integrity.

• Implement Clock Tree Synthesis (CTS) while optimizing skew, latency, and clock power.

• Direct IR/EM sign-off strategy, thermal analysis, and comprehensive physical verification of the entire chip.

• Integrate and validate low-power methodologies, including UPF/CPF flows.

• Collaborate with DFT and PD teams for scan insertion, Built-In Self-Test (BIST) structures, test modes, and timing.

• Coordinate with Packaging and SI teams on bump planning, floorplan constraints, and package-aware timing.

• Establish physical design quality standards, conduct design reviews, and ensure successful execution through tapeout.

• Provide technical leadership, mentorship, and guidance to junior and mid-level physical designers.

• Advocate for continuous improvements across flows, scripts, and design methodologies.

⛳️ Requirements

• Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field; an advanced degree is preferred for leadership positions.

• A minimum of 8 years of relevant experience in ASIC Physical Design.

• Proven track record of multiple tape-outs at advanced technology nodes, preferably from 16nm to 3nm.

• Extensive expertise in floorplanning.

• Extensive expertise in place and route.

• Extensive expertise in Clock Tree Synthesis (CTS).

• Extensive expertise in Static Timing Analysis (STA) and timing closure.

• Extensive expertise in physical verification and sign-off procedures.

• Extensive expertise in low-power design and UPF methodologies.

• Strong hands-on experience with Cadence and/or Synopsys physical design toolchains.

• Comprehensive understanding of RTL-to-GDS flows, design architecture trade-offs, and complexities of SoC integration.

• Capability to translate product requirements into physical design objectives, budgets, constraints, and deliverable plans.

• Excellent communication skills for conveying technical decisions across cross-functional teams.

• Ability to work effectively in a distributed team setting.

• Aptitude for managing schedules, deliverables, and quality in a dynamic development cycle.

• Outstanding analytical, debugging, and problem-solving skills with an acute attention to detail.

🏝️ Benefits

• Competitive salaries.

• Equity provided in the form of Incentive Stock Options (ISO).

• Employer-sponsored medical insurance plan.

• Health Savings Account (HSA) with employer contributions.

• Dental and vision reimbursement account (HRA).

• 401(k) retirement plan with employer matching.

• Flexible work location with options for remote work.

• Flexible time off.